USO0RE43236E

(19) United States (12) Reissued Patent

(10) Patent Number: US RE43,236 E (45) Date of Reissued Patent: Mar. 13, 2012

Vu et a]. (54)

(56)

AUTOMATIC CIRCUIT AND METHOD FOR

References Cited

TEMPERATURE COMPENSATION OF U.S. PATENT DOCUMENTS

OSCILLATOR FREQUENCY VARIATION 4,922,212 5,473,289 5,548,252 5,668,506 6,476,682 6,819,194 2004/0124937

OVER TEMPERATURE FOR A REAL TIME CLOCK CHIP

(75) Inventors: H0a Vu, Milpitas, CA (US); Teck-Boon

Serm, Freemont, CA (US); Bhupendra K. Ahuja, Freemont, CA (US)

A A A A B1 B2 A1

5/1990 12/1995 8/1996 9/1997 11/2002 11/2004 7/2004

Roberts et :11. IshiZaki et :11. Watanabe et a1. Watanabe et a1. Cole et :11. Toncich et a1. Han et al.

Primary Examiner * Vit Miska

(73) Assignee: Intersil Americas Inc., Milpitas, CA (Us)

(74) Attorney, Agent, or Firm * Fogg & Powers LLC

(57)

(21) Appl. No.: 12/779,885 (22) Filed:

An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator

May 13, 2010

block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry

Related US. Patent Documents

includes a non-linear capacitor DAC including a plurality of

Reissue of:

(64)

Patent No.:

Appl. No.:

7,371,005 May 13, 2008 11/818,387

Filed:

Jun. 14, 2007

Issued:

load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors

to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Ana log Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and

U.S. Applications: (60)

Provisional application No. 60/859,396, ?led on Nov.

the ATR bits. A temperature sensor block is coupled to the

16, 2006, provisional application No. 60/869,683,

crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for out

?led on Dec. 12, 2006.

(51)

Int. Cl. G04B 17/20 H03L 1/00

ABSTRACT

putting a digital temperature signal representative of the tem perature of the crystal. A DSP engine receives the digital temperature signal and calculates frequency correction

(2006.01) (2006.01)

(52)

US. Cl. ...................................... .. 368/202; 331/176

needed to correct for frequency inaccuracy and determines a bit sequence including the ATR bits appropriate to achieve the

(58)

Field of Classi?cation Search .................. .. 368/10,

frequency correction.

368/156, 159, 200*202; 331/66, 176, 158 See application ?le for complete search history.

35 Claims, 18 Drawing Sheets

115 110

105

Temperature Sensor

PTAT Generator /

PTAT Voltage

—>

DSP ADCout[9;0] F_ATR

F_DTR

TEMP 12:

Crysla r/u

1

/

12o

A

Crystal

\:|

Compensation

Capacitor

“-

Circuil

DAC

I25

5 Bit

"

X0

Digital Trim F32kHz

Logic 1H2

5*

ii

2

:

i7

Timed Trigger

.—_

1

1x0

RTC _l_/ Vsupply i

Rtgulnlor

US. Patent

Mar. 13, 2012

Sheet 1 of 18

US RE43,236 E

Temperature Drift: PPM Delta = - Alpha * (T - 25)"2

Typical Alpha=.034ppm/C"2

PM

Parabolic Temp Characterstics.

$00.0 / 4x410 K 4mm -.Mll?

4m 4m -zu 40 a

10 20 an 5m 50 w ‘m an‘

‘EEMFERATUERE PC;

FIG. 1:

RTC CRYSTAL TEMPERATURE DRIFT

(PRIOR ART)

US. Patent

Mar. 13, 2012

Sheet 2 0f 18

US RE43,236 E

Externa! XTAL

| | 0° ||

HCSI Ls Rs x1 pin INTERNAL

XOIFIN pin Rbias

CIRCUITRY

INTERNAL

,W

CIRCUETRY l

—— C2

37 FIG. 2(a): PIERCE OSCILLATOR

(PRIOR ART)

US. Patent

Mar. 13, 2012

Sheet 3 0f 18

US RE43,236 E

Crystal Oscillator ATR

-8-+< -

fs

=

1

—-—----

ZTTKILSCS fp ==

f5

1 +

CS

2(CL + Co) CU * GL2 CL '

cu + GL2

The frequency can be varied by changing CL.

110.2(1)) (PRIOR ART)

US. Patent

Mar. 13, 2012

Sheet 4 0f 18

US RE43,236 E

\

115 110 105

l

Temperature Sensor

PTAT Generator

/

_,

PTAT Voltage



I

,

0 Bit ADC —>

DSP

ADCout[9:0]

;

>

F_ATR

F_DTR

TEMP 122

Crysta X1

120

r/ZS

l 5 Crystal

I

6 Bi‘ /

Capacitor 4

|:| <- Compensation Circuit

XO

DAC

I

Digital Trim >

Logic

d

F32kHz 1H2

5

I

-]

5

5; Vsupply

V

Timed Trigger

'

Regulator

139

m

FIG. 3(a)

so

RTC ____/

US. Patent

Mar. 13, 2012

Sheet 6 0f 18

US RE43,236 E

can

:E>E

A%58m<.UQ0Z vboEuE m_

/ \a? w6.5m:

.\

2:0

EL

dE 3.“

Mob?m0u>

235:082

i+mu1ne2mg;

SJ

US. Patent

Mar. 13, 2012

Sheet 7 of 18

US RE43,236 E

6-bit Thermometer Decoder

Decoder

The detector generates controls for the switches associated with the capacitor DAC segments.

FIG. 4(b)

US. Patent

Mar. 13, 2012

Sheet 8 0f 18

FIG. 5(a)

US RE43,236 E

US. Patent

Mar. 13, 2012

Sheet 13 0f 18

(Odé 48

ATRS 1

Arm 1

ATR3 o

ATR2 o

ATR] 0

AIR!) 0

49 50

1 1

o o

o o

o 1

51

1

1 1 1

o

0

1

1 0 1

52 53 54 55 56

1 1 1 1 1

1 1 1 1 1

0 o 0 o 1

1 1 1 1 o

o o 1 1 o

o 1 0 1 o

57 513

1 1

1 1

1 1

0 0

0 1

1 0

59 6o 61 62 63

1 1 1 1 1

1 1 1 1 1

1 1 1 1 1

0 1 1 1 1

1 o o 1 1

1 0 1 0 1

FIG. 6(a)

(:2

c1 1.116

co 9001‘

2.04,»

1.02p

250p

1.2Sp

292p

1469

US RE43,236 E

CL(pF) 35.47

6611110111111‘) 21.647

fp (Hz) 32767426 32767391

36.34 37.24

22514 23.416

313.111

24.353

32767355 32767320

39.15 40.17 41.23 4233 43.48

25.322 26.343 27.402 28.506 29.658

32767285 32767.250 327157.214 32767.179 32767144

44.69 45.95 47.27 48.65 50.10

30.1162 32.122 33.441 34.1123 36.274

32767110 32767075

51.62 53.23

37.798 39.401

32767.040 32767.005 32766971 32766936 32766901

US. Patent

Mar. 13, 2012

Sheet 14 0f 18

US RE43,236 E

ATR trim

FM

ATRCOdQ

FIG. 6(b)

Correction In PPM A

22 3ppm

-63ppm

FIG. 6(c)

\ :

US. Patent

Mar. 13, 2012

US RE43,236 E

Sheet 15 0f 18

115

110

Temperature Sensor

/

/

PTAT Generator PTAT Voltage

_,_

Temperature in Kelvin

Temperature Clamp 0 Bit ADC

/ > ’

TEMP[9:1]

lmin, max]=-50:95]°C

ADCoutl9z0]

TEMP

‘7

j

v TEMPC[7:O] (TEMPO-T25)

"TEMPCA[6:0] ALPHA[6:O]

_

[01127]

-

_

7 ALPHA (TEMPC T25)

2

PROD[10:O] l? SHIFT » 10

(Divider by 2"’) ATRO|5:O]

Add SIGN Bit

select between

I‘STQHPW'

\

CPPM[10:O]

q

K“) DTRO[1:0]

IPPM[10:0]

_/‘V

'\>

/

1 43

l NPPM[10:O]

select among

‘32' °' 32 ppm

4

NPPM[10:0]

CURRENT-ATR

[S,X1,XU,D2,D1'D0,A4,A3,A2,A1,A0]

Current_ATR++

Current__ATR

/

Y

F_ATR

F_DTR

\< F_ATR?

' "

25 6 Bit

N Current_ATR-

Capacitor 4

M

Y Current_ATR > F_ATR?

<—— F32kHz

Digital Trimming and Real Time Clock

Divider Chain F32kHz

N

V CURRENT_ATR 1Hz

FIG. 7

US. Patent

Mar. 13, 2012

Sheet 16 0f 18

US RE43,236 E

a Q a @ aa QQ m w QQ Q = r.

NI:5:5“£2NEN5,i: ass”é2”5msN2.2

Q

25c 35d .55: a5: a2: 85d .35:

_ Q _ # Q Q _

a d s a d NE

at a: 2 QQQ

= Q a c =

//Q A V/# 4 L

E Z2

_ _ Q Q _ _ Q

a = Q = D

Q Q Q Q

E5H:2igm£2“=2:5

#3‘I5

GE

Ema

g g

US. Patent

Mar. 13, 2012

Sheet 18 0f 18

US RE43,236 E

Af(ppm )

30ppm -_

l

Oppm

I

3O cystal clock

31 ‘5 30 second second

FIG. 8(c)

F TIME

US RE43,236 E 1

2

AUTOMATIC CIRCUIT AND METHOD FOR TEMPERATURE COMPENSATION OF

being the frequency ?uctuation over temperature. The typical frequency stability of a crystal can be described by equation

(1) below:

OSCILLATOR FREQUENCY VARIATION OVER TEMPERATURE FOR A REAL TIME CLOCK CHIP

Where Af is in the total frequency variation in ppm; Afl- is the initial frequency tolerance at 250 C., which usually within the

Matter enclosed in heavy brackets [ ] appears in the original patent but forms no part of this reissue speci?ca

range of :32 ppm; or is the parabolic curvature constant of the

tion; matter printed in italics indicates the additions made by reissue.

typical value of 0.034 ppm/C2 for quartz; T is temperature in Celsius and T25 is 250 C. This parabolic frequency versus temperature characteristic is depicted in FIG. 1.

crystal, for the commonly used quartz watch crystal, or has a

Afl- is the constant frequency offset due to the manufactur

CROSS-REFERENCE TO RELATED APPLICATIONS

ing quality issues and aging of the crystal. The value of the second term in equation 1, (X(T—T25)2, is determined by a which is a characteristic of the particular crystalline material,

This application claims the bene?t of Provisional Applica

and the operating temperature. Both terms combined could

tion No. 60/859,396 ?led on Nov. 16, 2006 and Provisional

contribute to a frequency variation up to about 200 ppm. For

Application No. 60/869,683 ?led on Dec. 12, 2006, both entitled “AUTOMATIC CIRCUIT AND METHOD FOR TEMPERATURE COMPENSATION OF OSCILLATOR

20

a month’s time.

FREQUENCY VARIATION OVER TEMPERATURE FOR

It is well known to use load capacitors to adjust the parallel

A REAL TIME CLOCK CHIP”, both being incorporated by reference in their entireties into the present application. FIELD OF THE INVENTION

an RTC, 100 ppm in the frequency variation implies that there is about 120 seconds (about 2 minutes) of error at the end of

resonance frequency, f0, of crystal oscillators. This frequency, f0, has an inverse square root relationship to load capacitor 25

(CL) changes. For on-chip load capacitor designs, some known designs use switched capacitor arrays controlled digi tally by input code vectors. Such capacitor arrays are known

The invention relates to electronic devices, and, more par

as capacitor digital-to-analog converters (referred to as

ticularly, to timekeeping devices useful in personal comput

capacitor DACs, capacitive DACs or CDACs). A conven

ers and other consumer electronics, as well as networking 30 tional capacitor DAC comprises of an array of N capacitors

devices.

hooked in parallel with binary weighted values plus generally one “dummy LSB” capacitor. During the acquisition phase, BACKGROUND OF THE INVENTION

Personal computers typically include a clock/calendar that tracks the time of day, day, month, and year. Such a clock/

35

calendar has various uses such as time stamping ?les and

the array’s common terminal (the terminal at which all the capacitors share a connection) is connected to ground and all free terminals are connected to the input signal (Analog In or VIN). After acquisition, the common terminal is disconnected from ground and the free terminals are disconnected from

inserting dates into documents, such as letters and e-mails

VIN, effectively trapping a charge proportional to the input

both sent and received. The clock/calendar must be program

voltage on the capacitor array. Due to the binary weighting and conventional digital code used, in response to the applied

mable for setting or changing the date or time of day. A

40

digital input codes, such DACs provide a linear analog output

clock/calendar is typically implemented in speci?c hardware with a dedicated crystal oscillator to insure accuracy and a

(capacitance).

battery backup power supply to insure preservation of time keeping data during an interruption of the primary power

Some RTCs provide a digital calibration register that can be used to periodically adjust the time of day in discrete

supply. This is especially important with personal computers

45

which are frequently powered down.

to the expected frequency deviation at a speci?ed tempera

Crystals generally show frequency variation with tempera

ture. The effect is to move the 32.768 kHz parabolic curve up or down in an attempt to approach 0.0 ppm accuracy at a

ture resulting into several hundred ppm shift in their nominal

frequency. Most applications, in particular, a Real Time Clock (RTC), requires accuracy of the input clock to be within

50

+/—5 ppm over a temperature range of —40 to 850 C. in order to provide accurate time information to the user.

An RTC with a 32.768 kHz quartz tuning-fork crystal oscillator is currently the standard timekeeping reference for

amounts. This method does not attempt to alter the crystal

behavior, but instead, periodically adjusts the time according

55

desired temperature. This is accomplished by adding or sub tracting clock cycles from the oscillator divider chain. The number of clock pulses removed (subtracted for negative calibration) or inserted (added for positive calibration) is set by the value in the calibration register. By adding clock pulses, time is sped up (the crystal curve moves up). In con

most electronic applications. The RTC maintains the time and

trast, by subtracting clock pulses, time is slowed down (the

date by counting seconds, which requires an oscillator divider

crystal curve moves down).

chain to derive a 1 Hz clock signal provided by the 32.768 kHz crystal oscillator. The current time and date information is stored in a set of registers, which is generally accessed through a communication interface. Tuning fork type crystal oscillators are known to have both a frequency offset at room temperature and frequency varia tion over temperature, typically resulting into several hundred ppm frequency shift from their nominal frequency of 32.768 kHz. These frequency offsets can be broken into two portions, one being the initial frequency inaccuracy, with the other

Another method dynamically changes the load capacitance 60

to “trim” the crystal frequency. One known RTC circuit of this type includes a 6-bit capacitor DAC that provides a delta of 0.5 pF for each code which is used to trim the frequency. In such an arrangement, due to the well known nonlinear fre

quency to CL relationship, changing CL linearly results in a

nonlinear change in frequency. For precision applications 65

requiring better than :5 ppm precision over a normal operat ing temperature range, such a non-linear frequency trim

arrangement generally cannot meet the requirement.

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