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Explain ASIC design flow with neat Discuss the economics of ASIC.

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What are the choices of ASIC cell library?

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Explain.

What are the different I/O requirements? Explain. What are the goals and objectives for each of the ASIC physical desig;n steps.

b.

Explain KL algorithm. Explain iterative placement improvement algorithm.

a. b. c. d.

Explain the following in detail : Design checks used for VLSI Several issues between parallel architecture Different models to withstand EOS Eigen value algorithm.

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Explain CFI connectivity model with example. What are the several ways to terminate transmission lines?

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(trO Marks) Explain hierarchical design with suitable example. Explain vectored instances and buses for 16-bit D-latch and draw the diagram for 4-bit (10 Marks) D latch with cardinality.

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(20 Marks)

## ASIC Design Jan 2016 (2014 Scheme).pdf

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