K L University Department of Electronics and Communication Engineering Course Handout for IV Year B.Tech., PROGRAM A.Y.2016-17, I Semester Course Name
: ASIC Design
Course Code
: 13 EC 363
L-T-P structure
: 3-0-0
Course Credits
:3
Course Coordinator
: Ms S.Chandana
Course Instructors
:
Course Teaching Associates
:
Course Objective: This course focus on Understanding of different types of programmable logic devices, their architecture, routing and programming techniques, Go through a complete ASIC design flow utilizing an FPGA and Understand the different CAD tools used at each level. Course Rationale: This course is at the intersection of computer architecture, digital circuits, and CAD and is suitable for students emphasizing fundamentals as well as new paradigms that students pursuing careers in both research and industry. For students pursuing a career in the chip-design industry, the course will provide valuable design experience from architecture to digital circuits. Course Outcomes (CO): CO. No.: 1 2 3 4
CO Analyze different types of ASIC design methodologies and Different CPLD Architectures Develop Program of different logic circuits using HDL and Verilog Programming and analyze different types of Faults in logic circuits. Analyze ASIC design flow Analyze Physical design flow of ASIC, Extraction the final circuit
SO B
BTL 2
E
2
E E
2 2
COURSE OUTCOME INDICATORS (COI): CO. No.
COI- 1
COI – 2
1
Understand the Basics of VLSI and CMOS Design Rules and combinational and sequential logic cell
Analyzing of different types of ALTRA ASICs and Different types of XILINX ASICs working methodology and the ACTEL ACT
2
Analyzing the FPGAs , Altra FLEX Design systems Develop the VHDL and VERILOG simulation and and low level design language synthesis
3
Analyze the fault identification phenomenon, Fault Analyze the basics steps of system partitioning testing and detection, fundamentals of data path for ASIC’s
elements Analyze the partitioning to allocate and Place the Understand the Global routing and detailed components in ASIC routing process
4
SYLLABUS Types of Asics: Design flow - CMOS transistors CMOS Design rules - Combinational Logic Cell –Sequential logic cell Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort - Library cell design Library architecture. Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA -Altera FLEX - Altera MAX DC & AC inputs and outputs - Clock & Power inputs - Xilinx I/O blocks. Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000. Altera FLEX Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design language - PLA tools EDIF- CFI design representation. Synthesis and Simulation: Verilog and logic synthesis -VHDL and logic synthesis - types of simulation Boundary scan test - fault simulation - automatic test pattern generation. Data Logic Cells: Data Path Elements, Adders, Multiplier, Arithmetic Operator, I/O cell, Cell Compilers. FPGA partitioning - Partitioning methods. System partition: - floor planning - placement - physical design flow - global routing - detailed routing - special routing - circuit extraction - DRC. TEXT BOOK 1.M.J.S .Smith, " Application - Specific Integrated Circuits " - Addison -Wesley Longman REFERENCES BOOKS 1.S.D. Brown, R.J. Francis, J. Rox, Z.G. Uranesic, " Field Programmable Gate Arrays " -Kluever Academic Publishers, 1992. 2.Mohammed Ismail and Terri Fiez, " Analog VLSI Signal and Information Processing ", Mc Graw Hill, 1994. 3.S. Y. Kung, H. J. Whilo House, T. Kailath, " VLSI and Modern Signal Processing ", Prentice Hall, 1985.
COURSE DELIVERY PLAN:
SES.
CO
COI
1
1
1
2
1
1
3
1
1
4
1
1
5
1
2
6
1
2
TOPIC Basic concept of VLSI , types of ASICs , Existing libraries and available logic cells. Programmable devices, Field Programmable devices , Lambda based design rules Logic Gate design and fault estimation , Concepts of OAI, AOI, driving strengths Combinational logic cells and clocking, Adders, parity generator and checker CMOS transistors – small signal analysis Pull up and Pull down ratios, Junction, overlap capacitances Parasitic capacitances, Cell design and Library design, Logic Modules – Actel ACT - Xilinx LCA -Altera FLEX - Altera MAX DC & AC inputs and outputs - Clock & Power inputs - Xilinx
TeachingLearning Method
Evaluation Component
LECTURE
Test1, SEE
LECTURE LECTURE LECTURE LECTURE LECTURE
Test1, SEE Test1, SEE Test1, SEE Test1, SEE Test1, SEE
I/O blocks. Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 Flexible Architectures –ALTERA FLEX 8000, Interconnects and routing resources Cell arrays and Xilinx EPLD , Testing of the circuits – Boundary scan test Low level design language and Introduction to Verilog and logic synthesis.
7
1
2
8
2
1
9
2
1
10
2
2
11
2
2
Assignment, blocking statements and example programs
12
2
2
Introduction, analysis and applications of multiplexers, Logic synthesis, example programs
13
2
2
Behavioral and functional analysis and static timing analysis
14
3
1
15
3
1
16
3
1
Introduction to data-path elements
17
3
2
Adders, Shifters ,Multipliers
18
3
2
Arithmetic and logical unit, working principle
19
3
2
System partitioning, physical steps, FPGA partitioning
20
4
1
Size and number of asic’s in a specified place
21
4
1
Introduction to floor planning, goals and objectives of floor planning
22
4
1
Channel, power planning
23
4
2
24
4
2
25
4
2
Goals and objectives Detailed Routing and algorithms
26
4
2
Special routing, Circuit extraction and DRC in rout
Gate level, switch level and transistor level simulations and timing analysis, Introduction to faults Identification of faults , open circuit, short circuited and degradation faults, Fault simulation
Illustrate the Global routing and placement, goals and objectives of Placement Introduction to Routing , Goals and objectives of global Routing
LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE LECTURE
Test1, SEE Test2, SEE Test2, SEE Test2, SEE Test2, SEE Test2, SEE Test2, SEE Test3, SEE Test3, SEE Test3, SEE Test3, SEE Test3, SEE Test3, SEE SEE SEE SEE SEE SEE SEE SEE
Session Wise Teaching – Learning Plan Session Number: 1 Session Outcome: Explanation of course handout and Understand the Basic Concepts of VLSI. Time in MIN. Topic BTL Teaching – Learning Method 10 Introduction 1 Discussion 15 Course Handout Explanation 1 Oral 15 Examination Pattern 1 Oral 10 Quires and Answers on Topic – 1 1 A.L: - Think-pair-share 15 Basic concept of VLSI 1 Chalk and talk 15 VLSI Design flow 1 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - Think-pair-share 5 Conclusion & Summary 1 Discussion
Session Number: 2 Session Outcome: Understand Different types of ASICs and programmable devices Time in MIN. Topic BTL 10 Recap of previous session 1 Full custom and semi custom, Existing libraries and available 15 1 logic cells 15 Channeled and channel less gate arrays 1 10 Quires and Answers on Topic – 1 1 15 Programmable devices 2 15 Field programmable devices 2 10 Quires and Answers on Topic – 2 1 5 Conclusion & Summary 1
Teaching – Learning Method Discussion Chalk and talk Chalk and talk A.L: - Catch Up Chalk and talk Chalk and talk A.L: - Stump your partner Discussion
Session Number: 3 Session Outcome: Understand lambda based design rules and analyze different Combinational Logic Cells Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Lambda based rules 1 Chalk and talk 15 Connections and identifiers, VCC and VSS 2 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - Think-pair-share 15 Logic gates, Basic concept of AOI, OAI 1 Chalk and talk 15 Parasitic capacitances, faulty transistors etc., 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - Think-pair-share 5 Conclusion & Summary 1 Discussion Session Number: 4 Session Outcome: Analyze clocking of Sequential logic cell and design different Flip-Flops Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Driving strength 2 Chalk and talk 15 clocking single phase and multi phase 2 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - Group problem solving 15 Design of flip-flops and verify with clocked inverters 2 Chalk and talk 15 Full adder and half adder, Parity generator and checker examples 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - Group problem solving 5 Conclusion & Summary 1 Discussion
Session Number: 5 Session Outcome: Understand Transistor parasitic capacitance and calculate Pu and Pd ratios. Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Working in saturation region, small signal analysis 1 Chalk and talk 15 Overlap capacitance , Gate capacitance 1 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - Stamp your partner 15 Pull up and Pull down ratios. 2 Chalk and talk 15 Symbolic layouts 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - Group problem Solving 5 Conclusion & Summary 1 Discussion
Session Number: 6 Session Outcome: Analyze different Logic modules – XILINX, ACTEL Time in MIN. Topic 10 Recap of previous session 15 ACT1 AND ACT2 Logic module 15 ACT 3 Logic module 10 Quires and Answers on Topic – 1 Logic blocks and Architectures(XILINX - XC-4000 and XC5200), 30 symbolic layouts 10 Quires and Answers on Topic – 2 5 Conclusion & Summary
BTL 1 2 2 1
Teaching – Learning Method Discussion Chalk and talk Chalk and talk A.L: - Think-pair-Share
2
Chalk and talk
1 1
A.L: - Think-pair-Share Discussion
Session Number: 7 Session Outcome: Analyze Altra flex Architecture and different logics of Altera Time in MIN. Topic 10 Recap of previous session 30 Different types of flexible architectures 10 Quires and Answers on Topic – 1 30 Altra flex 8000 10 Quires and Answers on Topic – 2 5 Conclusion & Summary
BTL 1 2 1 2 1 1
Teaching – Learning Method Discussion Chalk and talk A.L: - Think-pair-Share Chalk and talk A.L: - Think-pair-Share Discussion
Session Number: 8 Session Outcome: Analyze Interconnects for Act-2 and Act-3 Time in MIN. Topic 10 Recap of previous session 30 Routing resources act2 interconnects 10 Quires and Answers on Topic – 1 30 act3 interconnects 10 Quires and Answers on Topic – 2 5 Conclusion & Summary
BTL 1 2 1 2 1 1
Teaching – Learning Method Discussion Chalk and talk A.L: - Think-pair-Share Chalk and talk A.L: - Think-pair-Share Discussion
Session Number: 9 Session Outcome: Understand and Analyses Xilinx LCA and EPLD Time in MIN. Topic 10 Recap of previous session 15 xilinx LCA 15 xilinx EPLD 10 Quires and Answers on Topic – 1 30 Review of complete1 10 Quires and Answers on Topic – 2 5 Conclusion & Summary
BTL 1 2 2 1 1 1 1
Teaching – Learning Method Discussion Chalk and talk Chalk and talk A.L: - Group Problem Solving Chalk and talk A.L: - Group Problem Solving Discussion
Session Number: 10 Session Outcome: Analyze Logic synthesis Time in MIN. Topic 10 Recap of previous session 15 Introduction to logic synthesis 15 Analysis of blocking and non blocking statements 10 Quires and Answers on Topic – 1 30 Example programs 10 Quires and Answers on Topic – 2 5 Conclusion & Summary
BTL 1 2 2 1 2 1 1
Teaching – Learning Method Discussion Chalk and talk Chalk and talk A.L: - Catch Up Chalk and talk A.L: - Group Problem Solving Discussion
Session Number: 11 Session Outcome: Analyze Multiplexers and write Code for Multiplexer Time in MIN. Topic 10 Recap of previous session 15 Introduction to multiplexer 15 Analysis of multiplexer 10 Quires and Answers on Topic – 1 30 Examples programs 10 Quires and Answers on Topic – 2 5 Conclusion & Summary
BTL 1 2 2 1 2 1 1
Teaching – Learning Method Discussion Chalk and talk Chalk and talk A.L: - Think-pair-Share Chalk and talk A.L: - Stump your partner Discussion
Session Number: 12 Session Outcome: Analyze different styles of Simulation styles, Analyze static timing analysis Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Behavioral simulations 2 Chalk and talk 15 Functional simulations 2 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - Think-pair-Share 15 Static timing analysis 2 Chalk and talk 15 Gate level simulations 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - quiz 5 Conclusion & Summary 1 Discussion
Session Number: 13 Session Outcome: Analyze Simulation styles, Programs for logic gates Time in MIN. Topic 10 Recap of previous session 15 Switch level simulations level 15 Transistor level simulations 10 Quires and Answers on Topic – 1 30 Example Programs for logic gates transistor 10 Quires and Answers on Topic – 2 5 Conclusion & Summary
BTL 1 2 2 1 1 1 1
Teaching – Learning Method Discussion Chalk and talk Chalk and talk A.L: - quiz Chalk and talk A.L: - Group problem solving Discussion
Session Number: 14 Session Outcome: Analyze different Fault models and Different simulation styles Time in MIN. Topic BTL 10 Recap of previous session 1 15 Identification of faults 2 15 Types of faults 2 10 Quires and Answers on Topic – 1 1 15 Open circuit, short circuited and degradation faults 2 15 Gate level, switch level and transistor level simulations 2 10 Quires and Answers on Topic – 2 1 5 Conclusion & Summary 1
Teaching – Learning Method Discussion Chalk and talk Chalk and talk A.L: - Think-pair-Share Chalk and talk Chalk and talk A.L: - Think-pair-Share Discussion
Session Number: 15 Session Outcome: Analyze the techniques to Test a logic circuit and fault identification. Time in MIN. Topic BTL 10 Recap of previous session 1 30 Introduction to vdd and vss testing 2 10 Quires and Answers on Topic – 1 1 Example Programs for faults identification and review of 30 2 complete CO2 10 Quires and Answers on Topic – 2 1 5 Conclusion & Summary 1
Teaching – Learning Method Discussion Chalk and talk A.L: - quiz Chalk and talk A.L: - quiz Discussion
Session Number: 16 Session Outcome: Analysis of Data path elements and writing programs for combinational circuits Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Introduction to data path elements 2 Chalk and talk 15 Adders, 2 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - catch up 15 Multipliers 2 Chalk and talk 15 Examples of HA and FA programs 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - Think-pair-Share 5 Conclusion & Summary 1 Discussion
Session Number: 17 Session Outcome: Analyze Multipliers and Shifters Time in MIN. Topic 10 Recap of previous session 15 Example Programs for Multipliers 15 Shifters 10 Quires and Answers on Topic – 1 30 Example Programs for Shifters 10 Quires and Answers on Topic – 2 5 Conclusion & Summary
BTL 1 2 2 1 2 1 1
Teaching – Learning Method Discussion Chalk and talk Chalk and talk A.L: - Think-pair-Share Chalk and talk A.L: - Think-pair-Share Discussion
Session Number: 18 Session Outcome: understand Arithmetic logical unit and analyze the principle and applications of ALU Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Introduction to ALU 2 Chalk and talk 15 Working principle of ALU 2 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - Think-pair-Share 15 Applications of ALU 2 Chalk and talk 15 Review of complete CO3 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - quiz 5 Conclusion & Summary 1 Discussion
Session Number: 19 Session Outcome: Analyze the methods of system partitioning and steps in physical design flow Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Introduction to system partitioning 2 Chalk and talk 15 Steps in physical design 2 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - quiz 30 Portioning methodologies 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - quiz 5 Conclusion & Summary 1 Discussion
Session Number: 20 Session Outcome: Analyze methodologies for placement and identify size and placement of ASIC. Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 30 Size and number of ASIC in a specified place 2 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - Think-pair-Share 30 Different placement methodologies 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - Think-pair-Share 5 Conclusion & Summary 1 Discussion
Session Number: 21 Session Outcome: Analyze the goals and objectives of Floor planning and different methods to measure the delay Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Introduction to floor planning 2 Chalk and talk 15 Goals and objectives of floor planning 2 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: -quiz 15 Floor planning tools 2 Chalk and talk 15 Methods to measure delay 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: -quiz 5 Conclusion & Summary 1 Discussion
Session Number: 22 Session Outcome: Analyze channel routing and Power planning in ASIC and methods for delay estimation Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Channel length 2 Chalk and talk 15 Power planning 2 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - quiz 15 I/O delays 2 Chalk and talk 15 methods for delay estimation in different logic circuits 1 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - quiz 5 Conclusion & Summary 1 Discussion
Session Number: 23 Session Outcome: Analyze the goals and objectives of Placement and methods for global and local placement. Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 30 Introduction to placements 1 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - Think-pair-Share 15 Goals of placement 2 Chalk and talk 15 objectives of placement 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - Think-pair-Share 5 Conclusion & Summary 1 Discussion Session Number: 24 Session Outcome: Analyze the Physical Design flow methods and routing techniques Time in MIN. Topic BTL 10 Recap of previous session 1 15 Flow for physical design 2 15 Methods for physical design 2 10 Quires and Answers on Topic – 1 1 30 Introduction to routing 2 10 Quires and Answers on Topic – 2 1 5 Conclusion & Summary 1
Teaching – Learning Method Discussion Chalk and talk Chalk and talk A.L: - Think-pair-Share Chalk and talk A.L: - Think-pair-Share Discussion
Session Number: 25 Session Outcome: Analyze the goals and objectives of Global routing, techniques for global and local routing Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Goals and objectives of routing 1 Chalk and talk 15 Global routing 1 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - stump your partner 15 Local routing 1 Chalk and talk 15 Methods for global routing 2 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - stump your partner 5 Conclusion & Summary 1 Discussion
Session Number: 26 Session Outcome: Analyze the methods for detailed routing of ASICs and review of concepts Time in MIN. Topic BTL Teaching – Learning Method 10 Recap of previous session 1 Discussion 15 Introduction to detailed routing 1 Chalk and talk 15 Methods of detailed routing 2 Chalk and talk 10 Quires and Answers on Topic – 1 1 A.L: - quiz 30 Review of complete CO4 1 Chalk and talk 10 Quires and Answers on Topic – 2 1 A.L: - quiz 5 Conclusion & Summary 1 Discussion
EVALUATION PLAN:
Evaluation Component
Weightage /Marks
Date
Duration
COI Number BTL
Test 1
Weightage (10%)
Test 2
CO2
Test 3
2
1
2
1
2
1
2
1
2
2
2
2
2
2
1
5
5
15
15 5
5
15
15 5
5
15
15
90 mts
90 mts
Max Marks (30)
Active Learning
Attendance
Weightage (5%)
Distributed uniformly among all sessions
Max Marks (25) Weightage (5%) Weightage (60%)
Semester End Exam
CO4
1
Max Marks (30) Weightage (10 %)
CO3
90 mts
Max Marks (30) Weightage (10 %)
CO 1
Max Marks (60) Question Number
3 hrs
6
6
6
6
6
6
12
12
6
6
6
6
6
6
12
12
1/2.a
1/2.b
3/4.a
3/4.b
5/6.a
5/6.b
7/8
7/8
Name of Faculty 1
S Chandana
Chamber Consultation Day(s) Saturday
Chamber Consultation Timings for each day 9:00 to 10:00 AM
Chamber Consultation Room No:
Signature of Course faculty
C218
Signature of COURSE COORDINATOR:
Recommended by HEAD OF DEPARTMENT:
Approved By: DEAN-ACADEMICS (Sign with Office Seal)
EVALUATION PLAN:
Evaluation Component
Weightage /Marks
Date
Duration
COI Number BTL
Test 1
Weightage (10%)
Test 2
CO2
CO3
1
2
1
2
1
2
1
2
1
2
2
2
2
2
2
1
5
5
15
15 5
5
15
15 5
5
15
15
90 mts
Max Marks (30) Weightage (10 %)
90 mts
Test 3 Max Marks (30)
Active Learning
Attendance
Weightage (5%)
1
1
1
2
Max Marks (25)
6
6
6
7
Weightage (5%)
Distributed uniformly among all sessions
Weightage (60%) Semester End Exam
CO4
90 mts
Max Marks (30) Weightage (10 %)
CO 1
Max Marks (60) Question Number
3 hrs
6
6
6
6
6
6
12
12
6
6
6
6
6
6
12
12
1/2.a
1/2.b
3/4.a
3/4.b
5/6.a
5/6.b
7/8
7/8