An Effective Implementation of the Compound Element Pseudo-transient Algorithm on SPICE3 Hong YU †a), Yasuaki INOUE†, Xiaochuan HU††, Kazutoshi SAKO† and Yun YANG† †

Graduate School of Information, Production and Systems, Waseda University †† Japan EDA technologies Innovation Inc a) E-mail: [email protected]

ABSTRACT The pseudo-transient analysis (PTA) method is an effective practical method for finding the DC operating point solutions of nonlinear circuits when the Newton-Raphson method fails. In this paper, an efficient implementation is proposed for the compound element PTA algorithm, which is based on the SPICE3 simulator without enlarging the circuit set of equations and the Jacobian matrix, since the compound element PTA algorithm has the advantage of effectively preventing from the oscillation problems in conventional PTA algorithms. Moreover, the convergence of this implementation is proved in principle in this paper. Also, the ability to avoid oscillation problems and the effective performances of our implementation are demonstrated by the examples. Keywords: Pseudo-transient analysis, DC operating point solution, SPICE3 implementation, compound element

1.

Introduction

Nowadays, the SPICE-like or SPICE-compatible simulator is definitely one of the most popular EDA tools for IC designers. They are extensively used in current commercial EDA software. As a result of sharing the same SPICE core, they all utilize the Newton-Raphson (NR) iterative algorithm to find DC operating point solutions of nonlinear circuits. Unfortunately the NR method may fail to converge to a solution unless a good initial guess sufficiently close to the solution is given [1]. However, the DC operating point is so fundamental in circuit simulation, which is regarded as the starting point for AC analysis, transient analysis and etc, that many practical methods come out to overcome this non-convergence problem, such as Gmin stepping, source stepping, pseudo-transient analysis (PTA) and so on [2]–[8], which are also widely used in these commercial SPICE-like simulator softwares. Moreover, the PTA method is regarded as a promising method compared with the other practical methods [3]. As for the conventional PTA algorithms, they can be categorized to two types [5]-[8]: the constant capacitor/ inductor PTA algorithm and the time-varying pseudocapacitor PTA algorithm. However, there is a fatal disadvantage. That is both of them may fail to converge to the DC operating point of the whole circuit due to the inevitable oscillation problems of some subcircuit structures. In order to improve the convergence properties, the novel compound element PTA algorithm is proposed in [2], which can avoid the oscillation problems effectively and also improve the simulation efficiency. In [2], the compound element PTA algorithm is implemented by modeling these compound pseudo-elements in the netlist method in the HSPICE simulator. Although the simulation results are able to be easily obtained by the netlist method, there are so many limitations from the SPICE-like

simulator which have to be obeyed. Among them, the timestep control problem is the most troublesome, which always results in simulation aborting from the process. Therefore, in this paper we aim to propose an implementation based on the SPICE3 simulator, which is able to obtain high simulation efficiency by not enlarging the circuit set of equations and the Jacobian matrix. At the same time, we can also take the advantage of easy modification, the efficient coding and direct touch to the SPICE core from the SPICE3 source program. Furthermore, this implementation is technique applicable

to general circuits. This paper is organized as follows. The conventional and the compound element PTA algorithms are summarized in Section 2. Then the new implementation for the compound element PTA algorithm is proposed in Section 3, including the new implemented stamps for the pseudo compound elements and the convergence consideration of this implementation. In Section 4, the high simulation efficiency of this new implementation is demonstrated by the examples. Also the ability of avoiding oscillation problems is proved again. Finally the conclusions are presented in Section 5.

2.

The Pseudo-transient Analysis Method

What is a PTA method? In short, when it is executed, certain pseudo-elements are firstly employed into the original circuit to form a new circuit. Then a transient analysis is done with an initial value of the new pseudo-circuit. When the pseudo-circuit finally reaches a steady state during the transient analysis, the solution at that moment is deemed as the DC solution of the original circuit. Here is the summery about the PTA method. [2]

2.1 PTA Method Equations Assume that the resistive portion of a target circuit can be expressed as Eq. (1)

F(x) = 0. (1) Then the DC operating points are solutions to Eq. (1). When the original circuit is modified to the PTA case, whatever the various pseudo-elements are, the common mathematical equations set on the PTA method can be written as F ( x(t ), x (t ), t ) = 0 x(t0 ) = x0 x (t )

t =tSETTLE

=0 ,

(2a ) (2b) (2c)

where x is the unknown variable vector, x is the derivative of x with respect to the time t, t0 is the start time of the transient analysis, x0 is the initial value of x at the time t = t0, and tSETTLE means the time when the circuits are settled down.

PTA method. Therefore, the compound element PTA algorithm is proposed to overcome the non-convergence problems, which is shown in Fig.3. The time-varying resistor RV is introduced in series with the constant capacitor C0, named Branch RVC as shown in Fig.3 (a). Similarly, the time-varying conductance GV is in parallel with the constant inductor L0 in the Fig.3 (b), named Branch GVL. Moreover, the variation of the value RV and GV is chosen to trace the curve as described in Fig.3 (c), which can be expressed as Eq.(3). The inserted positions are shown in Fig.3 (d)-(g). t /τ ⎪⎧GV (t ) = GV 0 e ⎨ t /τ ⎪⎩ RV (t ) = RV 0 e

.

(3)

2.2 Conventional PTA Algorithms In the constant capacitor/inductor PTA algorithm, the constant value capacitors/inductors are added to the original circuit when this PTA algorithm is processed. The inserted positions are shown as Fig.1.

Fig.3. The compound element PTA algorithm. (a) The Branch RVC. (b) The Branch GVL. (c) The varying curve of the RV/GV values. (d) - (g) The inserted positions of the compound pseudo elements.

Fig.1. The constant capacitor/inductor PTA algorithm. (a) The constant inductor in series with the voltage source. (b) The constant capacitor in parallel with the current source. (c) The constant capacitor inserted to the bipolar transistor. [2] As for the time-varying pseudo-capacitor PTA algorithm, the pseudo-capacitors with a variable value to time are employed, as shown in Fig.2 (b). They are inserted to each node and ground when processed.

Fig.2. The time-varying pseudo-capacitor PTA algorithm. (a) The time-varying capacitor. (b) The varying curve of the capacitor value. (c) The inserted positions of the capacitor. [2]

2.3 The Compound Element PTA Algorithm Because all energy-storage elements are removed away by treating capacitors as open circuited and inductors as short circuited during the DC analysis, there are no longer capacitors and inductors in the original circuit. However, the pseudo-elements are generally made up of capacitors or inductors. Owing to the insertion of the pseudo elements, it is possible for the new circuit to oscillate during the transient analysis, which inevitably leads to the non-convergence of the

3.

The Implementation in SPICE3 Simulator

In this section, the SPICE3 implementation without enlarging the original circuit set of equations and the Jacobian matrix is analyzed in detail. When the time-varying RV and GV are modeled with the controlled sources by the netlist method in [2], the Jacobian matrix of the modified circuit in the SPICE-like simulator is definitely enlarged since the additional nodes and controlled current/voltage sources are included. Obviously, it can result in a considerable calculation for VLSI circuit simulation, which is not so practical from this viewpoint. The simulation efficiency will be greatly challenged. Since the new implementation does not need additional nodes and equations, the simulation efficiency, even for VLSI circuits can be held at a relevant low level. Furthermore, although it is easy to obtain the simulation results by utilizing the netlist method in [2], there are so many limitations from the SPICE-like simulator, which have to be obeyed. Among these limitations, the most troublesome limitation is the problem of “internal timestep too small in transient analysis”, which is resulted from the especial timestep control algorithm of the SPICE-like simulator and directly causes the simulation aborting from the process. Therefore, the SPICE3 implementation is more developable compared with the temporary netlist method.

3.1 Implementation Description As a rewriting of SPICE2, SPICE3 offers the user great control and flexibility in performing simulations. Moreover, the coding is generally efficient since SPICE3 is written entirely in C language. Due to these advantages, the PTA subroutine in our implementation can be based on the original transient analysis subroutine [9] [10]. However, compared with the transient analysis, it is not necessary for the PTA method to include the consideration of the truncation error, the breakpoint and so on. As long as the modified circuit becomes steady state finally, the DC operating point of the original circuits is found. [2] The flow of the SPICE3 implementation for the compound element PTA algorithm is described as follows. Besides removing the unnecessary parts of the normal transient analysis, we need to add some new subroutines, which are including the matrix reloading for the modified circuit with compound pseudo elements, storing the old PTA state parameters, the initial condition setting, the judgment for the PTA convergence and etc. Moreover, the device structures and input/output interface are also modified for this PTA algorithm. Since the compound pseudo elements consist of two devices, the unknown variable number of the modified circuit is definitely enlarged when the netlist method is used for the PTA method. As shown in Fig.4 (a), the additional node k is added when the Branch GVL is inserted to the dependent voltage source. Moreover the current through the inductor iL is also added as another new variable to the modified circuit. Therefore, there are at least two additional variables and two additional equations due to the insertion of one Branch GVL except the time-varying conductance modeled by the voltage controlled current source [11] [12]. Similarly, it is also necessary for Branch RVC, as shown in Fig.4 (a), to add at least two new variables and equations. If there are NVS voltage sources, NCS current sources and NTR transistors in the original circuit, then the number NADD of the total additional variables reaches (4) N ADD = 2( NVS + NCS + 2 NTR ) . In other words, when the original circuit is a large scale, the Jacobian matrix of the modified circuit will be much larger than the original one. Obviously the simulation efficiency is greatly challenged. Further more, it is the most basic work to solve the n simultaneous linear equations in computer simulation. Due to the greatly increased variable number, although the sparsematrix technologies are utilized, the huge memory becomes necessary. Moreover, the structure of the sparse-matrix has to be built again, which makes the implementation more complex and extra simulation effort is needed. In order to improve the simulation efficiency, no additional variables and equations are needed in our implementation. The detailed analysis of the compound pseudo elements are given in the following subsection 3.2.

3.2 Stamps for Compound Element PTA Algorithm The Branch GVL and Branch RVC in Fig. 3 are redescribed in Fig.4 (a) and (b), respectively. In Fig. 4, each

pseudo-element is assumed to be inserted between node i and node j (as for Branch GVL, it is inserted in series with the voltage source, the additional node k and node j in fact). Also, ib and vb are the branch current and branch voltage, respectively. The current through the inductor L0 is iL and the voltage across the capacitor C0 is vc.

Fig. 4. Branch GVL/RVC in SPICE3 implementation. (a) Branch GVL. (b) Branch RVC. These pseudo-elements are analyzed as one whole part during our SPICE3 implementation. All the elements between the node i and the node j are regarded as the whole part and the node k is skipped over. We straight modify the Jacobian matrix according to the modified nodal approach without enlarging the matrix size at the same time. In SPICE, numerical integration is used to solve differential equations. There are three different numerical integration methods for use, backward Euler, trapezoidal and Gear methods. As for the PTA method, it is not necessary to pay much attention to the truncation error, timestep length and so on [2]. Considering about the tradeoff between the accuracy and stability of numerical integration, we use the backward Euler method for our implementation. Then the stamps of Branch GVL/RVC for Jacobian matrix reloading are analyzed as follows.

3.2.1

Branch GVL

As for Branch GVL in Fig. 4 (a), it is inserted in series with the independent voltage source. The relationship between ib and vb in continuous time domain can be expressed as Eq. (5) d [i (t ) − GV (t )(vb (t ) − E )] di (t ) vb = L0 L + E = L0 b +E dt dt dv (t ) dG (t ) dG (t ) ⎤ ⎡ di (t ) = L0 ⎢ b − GV (t ) b − vb (t ) V + E V ⎥ + E . dt dt dt dt ⎦ ⎣ (5) Resorting to the backward Euler numerical integration, the differential parts at the discrete timepoint tn+1 in Eq. (5) can be written as ⎧ dib (t ) I n +1 − I n = ⎪ dt , (6) hn +1 t =tn+1 ⎪ ⎨ V n +1 − V n ⎪ dvb (t ) ⎪ dt t =tn+1 = h n +1 ⎩ where hn+1 is the timestep value at tn+1. As for the time-varying conductance GV(t), due to Eq.(3), we have dGV (t ) GV 0 t /τ GV (t ) . (7) = e = τ τ dt Therefore, the numerical integration for GV(t) is expressed as Eq.(8)

dG (t ) G n +1 GV (t ) t =t = GV n +1 , V = V . (8) t = t dt τ n+1 n+1 Based on Eqs.(6) and (8), we can obtain the expression of the branch voltage V n+1 at tn+1,

the memory space. The size of the new Jacobian matrix is just the same as the one of the original circuit, which guarantees the simulation efficiency. TABLE 2 The stamp for Branch RVC.

−1

⎛h ⎛ h ⎞⎞ V n +1 = ⎜ n +1 + GV n +1 ⎜ 1 + n +1 ⎟ ⎟ * , τ ⎠⎠ ⎝ ⎝ L0 ⎛ n +1 ⎛ GV n +1 1 ⎞ ⎞ n +1 n n + ⎟ ⎟⎟ ⎜⎜ I + GV V − I + E * hn +1 ⎜ L0 ⎠ ⎠ ⎝ τ ⎝

(9) which can be rewritten in the form of V n +1 = Re q * I n +1 + Veq , (10) where −1 ⎧ ⎛h ⎛ h ⎞⎞ ⎪ Re q = ⎜ n +1 + GV n +1 ⎜ 1 + n +1 ⎟ ⎟ τ ⎠⎠ ⎝ ⎪ ⎝ L0 ⎨ ⎛ n +1 n ⎛ GV n +1 1 ⎞ ⎞ ⎪ n ⎪Veq = Re q * ⎜⎜ GV V − I + E * hn +1 ⎜ τ + L ⎟ ⎟⎟ 0 ⎠⎠ ⎝ ⎝ ⎩ . (11)

3.3 Convergence Consideration In this subsection, the convergence of the compound element PTA algorithm is proved. Consider Branch GVL as the example. We can rewrite Eq. (9) to Eq. (15) −1

⎛ h ⎛1 h ⎞ 1 ⎞ V n +1 = ⎜ n +1n +1 + 1 + n +1 ⎟ * hn +1 * ⎜ + *E n +1 ⎟ τ ⎠ ⎝ L0GV ⎝ τ L0GV ⎠ −1

⎛h ⎛ h ⎞⎞ + ⎜ n +1 + GV n +1 ⎜ 1 + n +1 ⎟ ⎟ * ( I n +1 − I n ) L τ ⎠⎠ ⎝ ⎝ 0

.

−1

Therefore, the stamp of Branch GVL is given in Table 1 corresponding to Fig. 4 (a).

⎛ h h ⎞ + ⎜ n +1n +1 + 1 + n +1 ⎟ *V n L G τ ⎠ ⎝ 0 V

(15)

TABLE 1 The stamp for Branch GVL.

When the mth timepoint tm is much greater than the value

τ during the PTA, the value Gm approaches to plus infinite. Gm = GV 0 exp(tm / τ ) . tm  τ ⎯⎯⎯⎯ ⎯ → Gm ≈ +∞

(16) Therefore, the factors of E, (Im-Im-1) and Vm can be approximate to Eq. (17) in the SPICE3 numerical implementation.

3.2.2

Branch RVC

Similarly, as for Branch RVC in Fig. 4 (b), we have the Eq. (12) in continuous time domain dv d [vb − ib * RV (t )] ib = C0 c = C0 . (12) dt dt di dR (t ) ⎤ ⎡ dv = C0 ⎢ b − RV (t ) b − ib V ⎥ dt dt dt ⎦ ⎣ Resorting to the similar analyzing method as Branch GVL, the branch current In+1 at tn+1 can be written as , (13) I n +1 = Ge qV n +1 + I eq

where −1 ⎧ ⎛ hn +1 hn +1 ⎞ ⎞ n +1 ⎛ . (14) ⎪⎪Ge q = ⎜ C + RV ⎜ 1 + τ ⎟ ⎟ ⎝ ⎠⎠ ⎨ ⎝ 0 ⎪ n +1 n n ⎪⎩ I eq = Re q * ( RV I − V ) Thus the stamp for Branch RVC in Fig. 4 (b) can be described in Table 2. Based on Table 1 and 2, it is easy to obtain the new Jacobian matrix for our compound element PTA algorithm in SPICE3 source program, where simple modification is enough without change the structure of the sparse-matrix and increase

−1

⎛ hm ⎛1 h ⎞ h 1 ⎞ + 1 + m ⎟ * hm ⎜ + ≈ m ⎜ m m ⎟ + L G L G hm τ τ τ 0 0 ⎝ ⎠ ⎝ ⎠

.

−1

⎛ hm hm ⎞ ⎞ m⎛ ⎜ + G ⎜1+ ⎟ ⎟ ≈ 0 τ ⎠⎠ ⎝ ⎝ L0 −1

−1

⎛ hm h ⎞ ⎛ h ⎞ + 1 + m ⎟ ≈ ⎜1+ m ⎟ ⎜ m L G τ τ ⎠ ⎝ ⎝ 0 ⎠ (17) Based on the relationship in Eq. (17), we have (V m − E ) = 1 + h1 / τ (V m−1 − E ) . m

(18) From the mth timepoint, the branch voltage VN at the Nth timepoint VN −E V N −1 − E =

Because

*

V N −1 − E V N −2 − E

*" *

Vm −E V m −1 − E

1 1 1 * *" * 1 + hN / τ 1 + hN −1 / τ 1 + hm / τ

.

(19)

1 1 1 , ," , < 1, 1 + hN / τ 1 + hN −1 / τ 1 + hm / τ

(20)

the right side of Eq.(19) can approach to zero, that is to say V N − E → 0 ⇒ V N → E . (21) Therefore, although Branch GVL is inserted to the voltage sources, its effect is disappeared finally. The compound element PTA algorithm is able to converge in this implementation. Moreover, if the value of hi/τ (i=m, m+1…, N) is increased, the convergence can be achieved more quickly. As for Branch RVC, we can obtain a similar prove about the convergence, and conclude like (22) IN → 0 . That means the convergence of Branch RVC is also assured. Therefore, the Eq. (2c) is satisfied.

4.

same parameters as the constant and time-varying PTA algorithms are used, which are summarized in Table 3, the simulation is also aborted from the process. The other output results are summarized in Table 4. In Table 4, TCPU means the consumed total CPU time for this simulation, #tot means the number of total iteration, and Err. msg is the error messages from HSPICE simulator.

Examples and Comparisons

In this section the comparisons of the compound element PTA algorithm with the conventional PTA algorithms and the implementation in SPICE3 simulator with the netlist method are demonstrated by examples. Fig.6. The simulation results of conventional PTA algorithm by the HSPICE netlist method.

Fig.5. The schematic of the example circuit. The ability to avoid oscillation problems of the compound element PTA algorithm has been shown in [2]. A new example circuit is presented as shown in Fig.5. This is a bipolar transistor invert chain circuit. There are five same substructures in series and A ~ F is the name of each node.

4.1 Effective Preclusion of Oscillation Problems The conventional PTA algorithms, constant capacitor/inductor PTA algorithm and time-varying capacitor PTA algorithm are implemented by the netlist method in HSPICE simulator. The output waveforms of each node in this example circuit are similar. Therefore, the waveform of the node F is chosen as the example, which is shown in Fig.6. Figure 6 (a) is the simulation result of the constant capacitor/ inductor PTA algorithm. The continuous oscillation is obviously observed. Also the waveform of the node F from the time-varying capacitor PTA algorithm is described as shown in Fig.6 (b), where the oscillation frequency becomes higher with the increasing time. Moreover, the transient simulation is aborted at the timepoint 2.50071ms due to the too small internal timestep. The compound element PTA algorithm is also implemented by this netlist method in HSPICE simulator. However, if the

TABLE 3 Parameters used for PTA algorithms. Compound PTA Constant Time-varying PTA PTA Netlist SPICE3 C0 (F) 0.0001 0.0001 0.0001 0.0001 L0 (H) 1 -1 1 Trise[8] -0.002 ---1E-4 1E-4 1E-4 τ(s) RV0(Ω) --100 100 GV0(S) --1E-5 1E-5 TABLE 4 HSPICE simulation outputs. Constant Time-varying Netlist PTA PTA Compound PTA TCPU(s) 0.12 780.71 -#tot 1296 8582803 -Err. msg -#1 #2 #1: **error** internal timestep too small in transient analysis time = 2.50071D-03; delta = 3.72529E-12; numnit =****** #2: **error** internal timestep too small in transient analysis time = 1.58691D-04; delta = 1.86265E-12; numnit = 945

4.2 Simulation Results of SPICE3 Implementation Our compound element PTA algorithm can not be finished for Fig.5 example by the netlist method in HSPICE, where the process is also aborted because of internal timestep problems. However, it can be well done in our SPICE3 implementation.

proved again.

Acknowledgment This work was supported in parts by funds from the MEXT via Kitakyushu and Fukuoka innovative cluster projects and the Grant-in-Aid for Scientific Research No.16360193 from the Japanese Ministry of Education, Culture, Sports, Science and Technology.

References Fig.7. The simulation result of the compound element PTA algorithm by SPICE3 implementation. The output of each node voltage based on the SPICE3 implementation in Fig.5 is presented in Fig. 7. The waveforms show that there are no oscillation problems at all, and the steady state is well achieved. Furthermore, the PTA final results are the same as the operating point from the original SPICE3. Furthermore, the hybrid voltage reference circuit is simulated with our SPICE3 implementation as another example, which consists of 10 BJT’s and 7 resistors [2]. The steady state is also well done. The two example outputs of the SPICE3 implementation are summarized in Table 5, where TConv is the PTA converged timepoint. We can see that the #tot becomes smaller compared with the one in [2]. TABLE 5 SPICE3 simulation outputs. Example Hybrid Voltage Circuit (Fig.5) Reference Circuit [2] TConv(s) 0.52768 0.02083 TCPU(s) 0.156 0.188 #tot 56 147 *Simulation conditions: Windows XP OS, 3 GHz CPU, 1 GB RAM

5.

Conclusions

In this paper, the efficient SPICE3 implementation without expanding the Jacobian matrix for the compound element PTA method has been proposed and analyzed. The simulation efficiency is obviously higher than the one of the netlist method. Moreover, this implementation can overcome the restriction of the netlist method based on other SPICE simulators. The outputs of the examples show that the PTA steady state can be well obtained. Also the compound element PTA algorithm’s ability of avoiding the oscillation problems is

[1] R. M. Kielkowski, Inside SPICE (Second Edition), McGraw-Hill, 1998. [2] H. Yu, Y. Inoue, Y. Matsuya, and Z. Huang, “An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits,” Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Kos, Greece, pp.1772-1775, May, 2006. [3] T. L. Quarles, “Analysis of performance and convergence issues for circuit simulation,” Univ. of California, Berkeley, CA, ERL-M89/42, April 1989. [4] L.W. Nagel, “Spice2: A computer program to simulate semiconductor circuits,” Univ. of California, Berkeley, CA, ERL-M520, May 1975. [5] W. Weeks, A. Jimenez, G. Mahoney, D. Mehta, H. Qassemzadeh, and T. Scott, “Algorithms for ASTAP–A network-analysis program,” IEEE Trans. Circuits and Systems, vol.20, no.6, pp.628-634, Nov. 1973. [6] R. Wilton, “Supplementary algorithms for DC convergence,” IEE Colloquium, SPICE: Surviving Problems in Circuit Evaluation, pp.3/1-3/19, June 1993. [7] E. Yilmaz and M.M. Green, “Some standard SPICE dc algorithms revisited: why does SPICE still not converge?” Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Orlando, Floride, vol.6, pp.286-289, May 1999. [8] L. Goldgeisser, E. Christen, M. Vlach, and J. Langenwalter, “Open ended dynamic ramping simulation of multi-discipline systems,” Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Sydney, Australia, vol.5, pp.307- 310, May 2001. [9] T.L. Quarles, “The SPICE3 Implementation Guide”, Univ. of California, Berkeley, CA, ERL-M89/44, April 1989. [10] T. Quarles, A.R. Newton, D.O. Pederson, A. Sangiovanni-Vincentelli, SPICE3 Version 3F5 User`s Manual, Univ. of California, Berkeley, Mar. 1994. [11] C.W. Ho, A.E. Ruehli, and P.A. Brennan, “The modified nodal approach to network analysis,” IEEE Trans. Circuits Syst., vol, CAS-22, no. 6, pp.504-509, Jun. 1975. [12] T.L. Pillage, R.A. Rohrer, and C. Visweswariah, Electronic Circuit & System Simulation Methods, McGraw-Hill, 1995

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