All-Optical Packet Router Based on MultiWavelength PPM Header Processing H. Le Minh – Student Member IEEE, Z. Ghassemlooy – Senior Member IEEE, FIEE, Wai Pang Ng – Member IEEE, and M. F. Chiang Northumbria University, UK

Abstract The paper proposes an all-optical 1×M router architecture based on pulse-positionmodulation header processing (PPM-HP) scheme for packet routing in all-optical highspeed wavelength division multiplexing (WDM) packet switching network. The router is mainly comprised of all-optical clock extraction, pulse-position-modulation header extraction, continuous-wave (CW) sources, wavelength conversion modules and a multiple-wavelength PPM routing table (MW-PPRT). The proposed MW-PPRT uses only a single-bitwise optical AND-gate to carry out fast correlation between the packet header and entire possible entries in the routing table. In addition, MW-PPRT offers the capability of simultaneously generating the routing table patterns for parallel header processing in PPM-HPs. The proposed router is investigated and simulated to show the ultrafast processing, wavelength routing and the optical signal-to-noise ratio (OSNR) performance. 1. Introduction The next generation optical network will rely on the all-optical header processing and switching technologies to provide continuous optical paths for packet routing to achieve high speed and high throughput data transmission. In recent years, a number of alloptical header processing and switching schemes have been developed such as alloptical self-routing [1], all-optical bypass router [2], all-optical label swapping [3] and alloptical routing based on the PPM header processing scheme [4]. In all-optical selfrouting, the address bits within the packet header field are extracted at the intermediate router to directly control the on/off states of the router optical switches. Although this scheme is relatively less complex, but it is not suitable for large scale networks because of increased header length for multiple-hop routing path. The all-optical bypass router offers higher transmission throughput by processing only a small subset of incoming header addresses, for packets with high probability routing path, in optical domain using a bank of all-optical mirror-based correlators. Whereas the remaining packets with addresses not included in the subset are processed in the main electronic router. Alloptical label swapping (AOLS) uses all-optical logic gates and wavelength conversion to process the header and switch packets, respectively. In AOLS scheme, packet header processing is based on the correlation between the packet header address and the generated address patterns (i.e. routing table entries). This correlation scheme suffers from a large delay due to (i) the exponential increase in the number of routing table (RT) entries with long header address and (ii) the response-time of the all-optical logic gates based on the nonlinear element (NLE) such as TOAD [5], UNI [6], SMZ [7], which depend on the NLE gain recovery time.

An alternative header processing scheme based on PPM-HP has been proposed in [4, 8], where the incoming packet-header address bits and the routing table entries are both converted into a PPM format before being compared with each other. The advantages of this scheme are (i) significantly reducing RT entries, (ii) using only a single bitwise AND gate for all address correlation, thus resulting in reduced address correlation time and avoiding the low response-time of all-optical logic gates, and (iii) offering multiple transmitting modes (unicast, multi-cast and broadcast) embedded in optical layer. In this paper, we further develop and adopt this processing scheme for WDM packet switching networks. The paper will introduce an all-optical WDM 1×M router based on the proposed PPM-HP scheme. The organization of this paper is as follows: after introduction, Section 2 introduces the architecture of the proposed router. The simulation results and discussions are presented in Section 3. Section 4 will conclude the paper. 2. 1×M PPM-based WDM Router 2.1 All-optical Core Network and 1×M PPM-HP-based WDM Router An all-optical core network with up to 16 edge nodes and a number of core routers (core nodes) K is shown in Fig. 1(a), with each edge node having a unique known decimal address from 0 to 15 (i.e. from 0000 to 1111 in binary format). In the core network, packets are routed from a source edge node to a target edge node via a defined shortest path through a number of core routers. At a source edge node, the incoming electrical low-speed data packets with the same target edge node are electro-optically converted and time-multiplexed onto an optical high-speed packet at bit rate of 1/Tb, where Tb is the data bit duration. Optical packets with different target edge-node addresses are separated into different wavelengths and simultaneously transmitted through the core network. The optical packet is basically composed of a clock pulse for packet synchronization at each intermediate core router, the 4-bit address which encodes the edge-node target address and the packet payload bits. At each intermediate core router, target edge-node destination address is detected and compared with all entries in the routing table before being forwarded in a dedicated path to the next router by converting the packet wavelength. On arrival of the optical packet at the target edge node, electrical low-speed data packets are restored and timedemultiplexed to forward to the dedicated user ends. The PPM-HP based router block diagram is in Fig. 1(b). The router comprises of M PPM-HP modules in combination with a common MW-PPRT, continuous wave (CW) laser sources and a number of WDM multiplexers and demultiplexers. At the router input, multi-wavelength (λ1, λ2 … and λM) packets are passed through a demultiplexer before being fed to a bank of PPM-HP modules. Each PPM-HP module mth (1 ≤ m ≤ M) is assigned to process the packets at a given wavelength λm. From each PPM-HP module mth, single pulse cm is input to the MW-PPRT to generate M PPM-formatted routing table entries E1, E2, …, EM (at λm), which are fed back to mth PPM-HP for correlation purposes. Following packet address correlation, in the mth PPM-HP, the packet wavelength is converted and applied to the optical multiplexers for selecting the dedicated router output, where signals at M wavelengths could emerge from each router output simultaneously.

110



0111

#12

#7





#9 1001



#10

#15

1010

Core network #11

1111

#8



1000

High-speed optical data packet

Core router

Edge node

1011

Low-speed electrical data packet

(a) PPM-HP 1 …

c1

E1 E2 E3 EM

… …

λM λ3λ2λ1

PPM-HP 2 Input WDM DEMUX





c2

EM E1 E2 EM-1

… … E2 E3 E4 E1 E1 E2 E3 EM

c1 c2 cM

WDM MUX

MWPPRT



λ2 λ3 …

… λ1

WDM

Output 1

MUX

WDM

Output 2

MUX



λM λ3λ2λ1

PPM-HP M cM

λ1 λ2 … λM

λM λ1 … λM-1



WDM

Output M

MUX



λM λ3λ2λ1 λM λ3λ2λ1



CW

(b) Figure 1: (a) All-optical WDM core network (b) Block diagram of the proposed WDM 1×M router based on PPM-HPs, a common MW-PPRT and assisted CW laser sources

2.2 Operation Principle of PPM-HP The PPM-HP module with M-output ports comprises of clock extraction module (CEM), PPM header extraction module (PPM-HEM), a bank of all-optical AND gates, all-optical flip-flop (AOFF) and wavelength conversion (WC) modules, see Fig. 2(a). Clock extraction from the incoming packet is carried out by using two cascading SMZ switches, see Fig. 2(b). In CEM, the first pulse (i.e. Clk – clock bit) from the input packet (at point (a)) is used as the control signals in SMZ-1 to open a narrow switching window (SW) for self extraction of the clock bit from the incoming packet, see point (b). However, the remaining pulses within the packets also generate switching windows contributing to the appearance of a number of residual pulses following the extracted clock pulse, thus reducing the on/off contrast ratio between the extracted clock and residual pulses. This ratio is improved by employing a second SMZ-2 to suppress the intensities of residual pulses (at point (c)) [9].

Outputs H Clk

Data

1

WC-1

Data packet, @λm H Clk

Data

WC-2



Input Da ta

Data

H

Clk

Data

H Ck



2

… M

WC-M

H Ck

xPPM(t)

1-N SP Converter

Clk

@λ2

PPM-ACM

Clock Extraction

λ1

AOFF 1

PPM-HEM

cSP

λ2

AOFF 2

x(t) &

c

& …



CW



N

AOFF M

2N×M switch matrix





1×2

λM

E1 E2 EM

& BPF BPF λ1 λ2

e1

ci

Address matches with entry 2

BPF λM

(Optionally) Could be changed to set new values of entries

eM

e2

(a) (a)

(d)

Clk

(c)

(b)

Data packet

SOA1 1×2

τin τSW

2×2

SMZ-2

τin τSW

1×2

SOA2

Polarization Controller (PC)

Amplifier

α

SMZ-1

2×2

SOA1

Polarization Beam Splitter (PBS)

2×2

SOA2

Attenuator

Optical delay

(b)

(e) TON

TLoop S’

} a0 a1 a2 a3

SET

1-N SP Converter SMZ3 SMZ2 SMZ1 SMZ0

TLoop

a3 a2 a1

CW

a0

cSP x(t) Switch (0)

PPM-ACM

2

1

Switch (1)

3

2 ×TS

2 ×TS

Switch (2)

2 ×TS

Switch (3)

Q

SOA1

PCW

SOA2

TLoop 0

2 ×TS

PFBL

β:(1 – β)

R’

xPPM(t)

RESET

(c) (f) Figure 2: (a) Diagram of a 1×M PPM-based multi-wavelength router, (b) inline clock extraction module, (c) PPM-HEM, (d) Diagram of MW-PPRT, (e) MW-PPRT for N =4, M = 3 and (f) AOFF

The principal operation of PPM-HP module is based on the PPM-HEM where the binary-formatted N-bit address is converted to a single pulse in a PPM-formatted 2N-slot frame. The pulse position is specified by the decimal value of N-bit address:

⎛ N −1 ⎞ xPPM (t ) = x⎜ t + ∑ ai × 2i × Ts ⎟, ⎝ i =0 ⎠

ai ∈ {0,1}

(1)

where x(t) and xPPM(t) are the input and output signals at the PPM address conversion module (PPM-ACM), respectively. The bit ai (0 or 1) is the ith bit in N-bit address, Ts is a defined PPM-slot duration. The conversion process is realized by a series of 1×2 switches shown in Fig. 2(c) [8]. The MW-PPRT stores the shortest-path information in the 2N×M switching matrix by setting the appropriate delays and connections, see Fig. 2(d). The single pulse cm (at λm) from the mth PPM-HP module is applied to MW-PPRT to generate M PPRT-entries E1, E2, …, EM [4]. In each entry Ek at λm (1 ≤ k ≤ M) with duration of 2N×Ts, there are a number of pulses whose locations correspond to the decimal metrics of address

patterns assigned for packet being switched to the kth output of the router. An example of MW-PPRT with N = 4, M = 3 is shown in Fig. 2(e). In MW-PPRT, if the incoming packet address matches with 0, 1, 2, 5, 8, 12, 14, or 0, 3, 7, 10, 13, 15 or 0, 1, 4, 6, 9, 11, the packet will be switched to the router output ports 1, 2 and 3, respectively. Note that the shift in the order of feeding entries to the individual PPM-HP module, see Figs. 1(b) and 2(a), is to ensure that PPM-HP modules do not switch signals with same wavelength to the same router output. In MW-PPRT, if a pulse appears in the same location in more than one entry, then the incoming packet is switched to multiple outputs of the router (i.e. multicast and broadcast). The correlation between the converted PPM-formatted address and M entries is implemented using a bank of M all-optical SMZ-based AND gates. Since only one AND operation is required, the header processing time is 2N×Ts [4]. The matching output from the kth (1 ≤ k ≤ M) AND gate is applied, at point SET, to the kth AOFF for setting it to ON state during a single packet duration TON, see Fig. 2(f). The AOFF is based on a single SMZ and a feedback loop (delayed by TLoop) to ensure that the ON state is maintained when the matching short pulse at the SET input exits the SMZ. During TON period, a CW signal (Q) from the kth AOFF at λk is fed to the WC-k for switching packet to the kth output port of PPM-HP module. The wavelength conversion module is based on a single SMZ given in [10]. 3. Simulation Results and Discussions The operation principle and OSNR performance of the router are demonstrated by numerical simulation using the Virtual Photonic Inc. (VPI) simulation software. The router simulation model is based on Figs. 1(b), and 2. The main simulation parameters used are given in Tables 1 and 2. Each packet contains one clock bit, N = 4 address bits and a long payload. Packets at wavelength λ1, λ2 and λ3 are applied to the router (three packets are transmitted in each wavelength) having high input OSNR of ~30 dB. Packet header addresses (in decimal values) are listed in Table 3 where the number m in brackets indicates that packet will be switched to the mth router output with the routing information given in Fig. 2(e). Table 1: Simulation system parameters

Table 2: SOA parameters

Table 3: Addresses of the incoming packets to the router

Figure 3(a) shows the packet waveforms at the router input. In the insets shown are packets at three different wavelengths before being multiplexed. Figure 3(b) top-leftinset displays the optical power spectrum of the input packets showing different wavelength components. The extracted clock pulses in the PPM-HP modules are shown in the remaining insets of Fig. 3(b). Note the high on/off contrast ratio of ~25 dB for the clock pulses. The signal waveforms presented in Figs. 3(c), (d) and (e) correspond to the multiplexed signals at the router outputs 1, 2 and 3, respectively. The intensity variations in these signals are due to presence of overlapping switched packets signals from all PPM-HP modules. Insets of the Figs. 3(c), (d) and (e) show signals with different wavelengths at the input of the multiplexers of the router outputs 1, 2 and 3, respectively. The overshot seen at the start of the switched signals is due to the transient process associated with rapid changes in the carrier density of the semiconductor optical amplifier (SOA) [11] in the SMZ of the WC. The insets for PPMHP 2 in Figs. 3(c) and (e) show packet with address of 1 (in decimal) being routed to the router outputs 1 and 3 (i.e. multicast transmission). λ1

Clk 1

λ2

λ3

(a)

Clk 3

Clk 2

(b) PPM-HP1 – Output λ2

PPM-HP1 – Output λ1

PPM-HP2 – Output λ2

PPM-HP2 – Output λ3

PPM-HP3 – Output λ3

(c)

PPM-HP3 – Output λ1

(d)

PPM-HP1 – Output λ3

λ3

λ2

λ1

PPM-HP2 – Output λ1

PPM-HP3 – Output λ2

(e)

(f)

Figure 3: (a) Input packets applied to the router, insets: packets at separate wavelengths, (b) input signal spectrum and extracted clock pulses, (c) router output 1, insets: packets to output 1 before being multiplexed, (d) router output 2, insets: packets to output 2 before being multiplexed, (e) router output 3, insets: packets to output 3 before being multiplexed and (f) power spectrum at the router output 1

The power spectrum at the output 1 of the router showing the two main wavelengths, λ2 (from PPM-HP 2) and λ3 (from PPM-HP 3), are displayed in Fig. 3(f). Also shown is the noise presented as the bar levels. From the graph, the OSNR (between the signal and noise level) is observed more than 20 dB. 4. Conclusions The paper has presented the architecture, operation and performance of all-optical 1×M router for WDM core network. The router has non-blocking characteristic due to employing parallel processing of incoming packet using a bank of PPM-HP modules and a common MW-PPRT. PPM header processing scheme offers fast correlation time (80 ps with the given system parameters) and avoids the speed limitation imposed by the NLE-based optical AND gates. Simulation carried out illustrates that packet are switched from a single input to multiple outputs with high OSNR of > 20 dB. Further work is in progress to improve the proposed router and construct a multiple-input-tomultiple-output router based on multi-wavelength PPM header processing. References [1] [2] [3]

X. C. Yuan, V. O. K. Li, C. Y. Li, and P. K. A. Wai, "A novel self routing address scheme for all optical packet switched networks with arbitrary topologies," IEEE Light. Tech., vol. 21, pp. 329-339, 2003. A. E. Willner, D. Gurkan, A. B. Sahin, J. E. McGeehan, and M. C. Hauer, "All-optical address recognition for optically-assisted routing in next-generation optical networks," IEEE Opt. Comm., pp. S38-S44, 2003. D. J. Blumenthal, B. Olsson, G. Rossi, T. E. Dimmick, L. Rau, M. Masanovic, O. Lavrova, R. Doshi, O. Jerphagnon, J. E. Bowers, V. Kaman, L. A. Coldren, and J.

[4] [5] [6] [7] [8] [9] [10] [11]

Barton, "All-optical label swapping networks and technologies," IEEE Light. Tech., vol. 18, pp. 2058-2075, 2000. H. Le-Minh, Z. Ghassemlooy, and W. P. Ng., "A novel node architecture for all-optical packet switched network," proc. of NOC2005, London, UK, pp. 209-216, 2005. T. Houbavlis and K. E. Zoiros, "Ultrafast pattern-operated all-optical Boolean XOR with SOA assisted Sagnac switch," Opt. Eng., vol. 42, pp. 3415-3416, 2003. S. A. Hamilton and B. S. Robinson, "40 Gb/s all-optical packet synchronization and address comparison for OTDM networks," IEEE Pho. Tech. Lett., vol. 14, pp. 209-211, 2002. R. P. Schreieck, M. H. Kwakernaak, H. Jackel, and H. Melchior, "All optical Switching at multi-100-Gb/s data rates with Mach-Zehnder interferometer switches," IEEE Quan. Elec., vol. 38, pp. 1053-1061, 2002. H. Le-Minh, Z. Ghassemlooy, and W. P. Ng., "Ultrafast header processing in all-optical packet switched-network," proc. of ICTON2005, Barcelona, Spain, vol.2, pp. 50-53, 2005. H. Le-Minh, Z. Ghassemlooy, and W. P. Ng, "Ultrafast all-optical self clock extraction based on two inline symmetric Mach-Zehnder Switches " proc. of ICTON2006, Nottingham, UK, Mo.P.16, 2006. Y. Ueno, S. Nakamura, H. Hatakeyama, T. Tamanuki, T. Sasaki, and K. Tajima, "168Gb/s OTDM wavelength conversion using an SMZ-type all-optical switch," presented at ECOC 2002, Munich, Germany, 2000. H. J. S. Doren, X. Yang, D. Lenstra, H. Waardt, G. D. Khoe, T. Simoyama, H. Ishikawa, and T. Hasama, "Ultrafast gain and index in SOA - theory and experiment," proc. of SPIE - Physics and Simulation of Optoelectronic Devices XI, San Jose, California, USA, 2003.

Author details The authors are with the Optical Communications Research Group, School of Computing, Engineering and Information Sciences, Northumbria University, Ellison Building, NE1 8ST, Newcastle upon Tyne, UK Email: {h.le-minh,fary.ghassemlooy,wai-pang.ng,ming-feng.chiang}@unn.ac.uk Phone: +44 (0)191 227 4902, Fax: +44 (0)191 227 3589

All-Optical Packet Router Based on Multi- Wavelength ...

2.1 All-optical Core Network and 1×M PPM-HP-based WDM Router. An all-optical core network with up to 16 edge nodes and a number of core routers (core nodes) K is shown in Fig. 1(a), with each edge node having a unique known decimal address from 0 to 15 (i.e. from 0000 to 1111 in binary format). In the core network,.

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