A Large Current and High Speed Laser Diode Driver Using Switch Position Modification Yun Yang∗, Jia Guo, Yasuaki Inoue and Hong Yu Graduate School of Information, Production and Systems Waseda University, Kitakyushu-shi, 808-0135 Japan ∗ Email: [email protected]

Abstract— This paper describes how to realize the high speed laser diode driver (LDD) circuit with high performance signal and large output current to drive the laser diode device. Based on the introduced idea of “Switch Position Modification (SPM)”, two types of LDD circuit architectures, including “Combination Switch Mode (CSM)” and “Source Follower Mode (SFM)”, have been proposed to satisfy the output signal requirements. Under the corresponding design specification, the CSM architecture was selected to realize the effective LDD circuit design. Moreover, the signal integrity problems, such as overshoot, undershoot and slew-rate, have also been improved in the new CSM architecture. In addition, appropriate transistor size selection and circuit combination can further amend the signal waveform. The LDD circuit was realized in a 0.6-µm CMOS technology. And the output current can reach several hundred milliampere with good signal integrity in the experimental simulation results. Thus the introduced “Switch Position Modification” idea and the proposed “Combination Switch Mode” architecture assure the high performance LDD circuit realization and signal output.

I. I NTRODUCTION Laser diode driver (LDD) is widely used in our life, such as the magneto optical devices, CD-R/RW, DVD-ROM/Player and laser printer digital PPC [1]. With the development of high capacity CD/DVD technology, the large current and high speed laser diode driver becomes one of the core elements in the electronics products. Thus many companies and researchers focus their efforts on this area and work hard to realize the high performance laser diode driver design [2]. Commonly, the signal integrity problem occurs in the laser diode driver design because of the large current and high speed output requirements. Overshoot/undershoot and slew-rate (rise time and fall time) are the main integrity problems in the LDD output waveform [3], [5]. Moreover, the signal waveform deficiency problem (or the sag problem) due to the channel interference also influences the output results and increases the difficulty of the LDD circuit design. Thus how to get the effective large current and high speed LDD circuit for laser driver applications becomes one of the crucial challenges in the recent consumer electronics products. The conventional LDD circuit uses current mirror structure with the switch insertion in the output current route, which can not easily send out good output waveform and keep the signal integrity, as other interface driver circuits and charge pumps used in VCO or PLL [4]. Thus many techniques have been employed to amend the overshoot/undershoot/slew-rate fault, compensate the sag problem and improve the output results [5]–[9].

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In this paper we introduce the idea of “Switch Position Modification (SPM)” to send out large current and improve signal integrity. New LDD switch architectures have been proposed and the corresponding characteristics are also given for further discussion and comparison. Then the proper switch circuit design and the source follower architecture are also used to increase the driver capability and amend the signal results when the SPM idea has been adopted. Finally, based on the design specification and performance reliability, the suitable LDD circuit design of “Combination Switch Mode (CSM)” architecture has been realized to drive the laser diode device with high performance signal and large output current. This paper is organized as follows. The LDD architecture and the detailed problems are discussed in Section II. Section III proposes the new idea of “Switch Position Modification”. The specific circuit architecture and corresponding design principle are analyzed in Section IV. Then Section V presents experimental results and discussions. Finally the conclusions are given in Section VI. II. P ROBLEM F ORMULATION In this paper our target is the effective design of large current and high speed laser diode driver used in the LDD circuit. The LDD architecture is given in Fig. 1 and the “Laser Diode” in this figure means the laser diode device. Because the output of the LDD circuit is used to drive the laser diode, the driver part should send out large current waveform and keep signal integrity. The logic part controls the driver input value and determines the driver function. Based on the control signal the LDD reads, erases and writes the information on the storage disc. And the different types of the function signals compose the final output waveform with good signal integrity.

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Fig. 1.

The LDD architecture and output signal waveform.

(a) Overshoot/Undershoot of on-chip test. Fig. 2.

(b) Slew-rate and Sag of on-chip test.

(c) Simulation result for output signal waveform.

The signal integrity problem in large output current situation of the conventional LDD circuit.

Fig. 2 shows the problems in the large current situation. Because the laser diode device connected to LDD circuit needs large current to ensure the laser output, the driver output current is not small and the signal waveform must keep high performance. The sizes of switch transistors which import the input LDD read/erase/write information are also not small to pass the required large current. Then the parasitic parameters of the switch transistors are large and the corresponding parasitic effects are also serious, especially in fast switch on/off situation of the high speed LDD design. Thus the signal integrity, including overshoot, undershoot and slewrate, has also been influenced as shown in Fig. 2. Moreover, the sag problem is caused by the channel interference in the multi-channel LDD circuit. For example, the read channel, erase channel and write channel send out their own signals and compose the final output waveform (Fig. 1). Then the interaction of different channels causes the deficient waveform in the edge of output signal as shown in Fig. 2(b). The large output current also raise the severity of sag problem because of the increasing parasitic effects. Thus how to deal with the large current situation to get high performance output drive signal becomes one of the important challenges in the recently LDD circuit designs. In this paper we focuses on the one channel output waveform improvement and do not consider the multichannel sag problem temporarily. III. S WITCH P OSITION M ODIFICATION In the LDD circuit the output stage to drive the laser diode device is realized by a current mirror architecture because of the large output current requirement. And to increase the drive ability, the current mirror is mainly composed of PMOS transistors as shown in Fig. 3(a). Because the PMOS transistors operate in the saturation region for the current mirror, the inside reference current Iref and output signal current Iout are given by [7] Iref = ID6 =

µp ·Cox W6 · ·(VGS6 − VT )2 ·(1 + λ·VDS6 ). (1) 2 L6

Iout = ID7 =

µp ·Cox W7 · ·(VGS7 − VT )2 ·(1 + λ·VDS7 ). (2) 2 L7

Iref =

µp ·Cox W6 · ·(VGS6 − VT )2 . 2 L6

µp ·Cox W7 · ·(VGS7 − VT )2 . 2 L7 Because of equal gate-source voltages in Fig. 3(a): Iout =

VGS6 = VGS7 ,

(3) (4)

(5)

We can obtain the current ratio between Iref and Iout from Eq. (3) and Eq. (4): Iout W7 /L7 W7 L6 = = , Iref W6 /L6 W6 L7 or Iout =

W7 /L7 Iref . W6 /L6

(6)

(7)

Then with the current mirror, the reference current Iref inside the LDD circuit can be copied to the output current Iout by the specific W/L ratio. The large output current requires big W/L size in the output stage, and the small reference current Iref reduces the power consumption and decrease the corresponding W/L size. Thus the W/L ratio between the current mirror of the output stage is very large, in common varying from 100 to 1000. And the MOS transistor in the output route, such as ‘M7’ in Fig. 3(a), is also increased to large size, even up to several millimeter for width. With the size increasing, the influences of parasitic effects can not be ignored easily. For the output MOS transistor ‘M7’ in Fig. 3(a), the main parasitic capacitances CGS7 and CGD7 are given as [10] CGS7 = CGSO(Wef f 7 ) + 0.67Cox(Wef f 7 )(L7ef f ), CGD7 ∼ =CGDO(Wef f 7 ),

(8) (9)

Where Wef f 7 and Lef f 7 mean the effective channel width and length in saturation situation. And CGSO is the overlap capacitance between gate and source overlap. Also CGDO is gate-drain overlap capacitance. Then we can get

If channel-length modulation is neglected, we can get [7]

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CGS7 ∝(Wef f 7 ),

(10)

CGD7 ∝(Wef f 7 ).

(11)

and

Moreover, the proposed SPM method can also improve the charge/discharge characteristics and ameliorate the signal integrity performance further. For example, the “Parallel Switch Mode (PSM)” supplies an additional discharge route to release the accumulated charge and drop the output waveform quickly. The broken line in Fig. 3(a) gives the discharge route as M 7 Source⇒V DD⇒P arallel Switch⇒M 7 Gate. (12) For the “Series Switch Mode (SSM)”, it uses the low inside current to charge the driver transistor and decrease the overshoot/undershoot influence. And the detailed charge route is shown by solid line in Fig. 3(a): (a) The switch insertion positions and charge/discharge routes.

V DD⇒M 7 Source⇒M 7 Gate⇒Series Switch⇒ M 8 Source⇒M 8 Drain⇒GN D. (13) Thus the introduced idea of “Switch Position Modification (SPM)” can provide an effective method to solve the large output current problems in the high speed LDD circuit. The output waveform can also be meliorated greatly by the SPM method. Based on the idea, many specific LDD circuits have been proposed to realize the high performance driver design.

(b) Series switch mode (SSM).

(c) Parallel switch mode (PSM).

IV. P ROPOSED LDD C IRCUITS Fig. 3. The “Switch Position Modification (SPM)” description and the switch insertion mode examples (SSM and PSM).

Consequently the parasitic capacitances increase with the transistor size rising. Then the parasitic effects also raise and impact the driver performance. Thus how to abate the parasitic effects in large current driver design becomes the crucial problem of the LDD circuit design. In the conventional LDD circuit, the input signal of read/write/erase information is imported by the switch transistor, which is inserted in the output current route. In Fig. 3(a) the twill box gives the conventional insertion position of the input signal switch. However, the large switch current, which drives the laser diode, will aggravate the parasitic effects and influence the output signal integrity, especially in fast switch on/off situation as the above analysis. Thus we introduce a new idea of “Switch Position Modification (SPM)” to improve driver performance. The new SPM method moves the input signal switch from the conventional output current route to other possible switch insertion positions, such as the inside reference current route. The shadow boxes in Fig. 3(a) show the possible switch positions, including the parallel switch position (horizontal texture box) and series switch positions (vertical texture boxes). The corresponding examples of “Series Switch Mode (SSM)” and “Parallel Switch Mode (PSM)” are also given in Fig. 3(b) and Fig. 3(c). After the SPM method is used, the fast switch on/off current has been decreased rapidly because the inside current is much smaller compared with the output current. Then the transistor sizes and the parasitic effects have also been reduced to improve the signal integrity. Additionally the chip area and the power consumption can also be amended by the smaller MOS W/L size and more compact LDD circuit design.

Based on the proposed idea of “Switch Position Modification (SPM)”, we tested all the possible switch insertion positions or switch combination types. Then two possible LDD architectures, including “Combination Switch Mode (CSM)” and “Source Follower Mode (SFM)”, are presented to satisfy the requirements of large current and high speed LDD design. A. Combination Switch Mode (CSM) The different LDD architectures based on relevant switch insertion positions can cause the system performance variety. We unite the merits of small charge current in “Series Switch Mode (SSM)” (Fig. 3(b)) and quick waveform drop in “Parallel Switch Mode (PSM)” (Fig. 3(c)). Then we get “Combination Switch Mode (CSM)” architecture, including parallel&series switches, to send out high performance signal (Fig. 4). When the series switch ‘M9’ is on, the parallel switch ‘M5’ is off in the “Combination Switch Mode”. Then the charge route is formed as the solid line in Fig. 4 and the route description is listed in Eq. (14), which charges the large size output stage transistor ‘M7’ by the small current Iref inside the LDD circuit. Because the fast switch on/off occurs in the small current route, the parasitic effects can be reduced rapidly and the signal performance can be improved greatly. V DD⇒M 7 Source⇒M 7 Gate⇒M 9 Source⇒ M 9 Drain⇒M 8 Source⇒M 8 Drain⇒GN D. (14) When the series switch ‘M9’ is off, the parallel switch ‘M5’ is on by the inverse gate input signals. Then the charge route through ‘M9’ is closed and new discharge route is constructed as the broken line in Fig. 4 and the detailed route in Eq. (15). Thus the accumulated charge in the output stage transistor ‘M7’ can be released quickly and the fall down speed in the

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Fig. 4.

The “Combination Switch Mode (CSM)” LDD architecture.

Fig. 5.

output waveform can be accelerated rapidly. So the slew-rate performance is much better than previous LDD results (Fig. 2). M 7 Source⇒V DD⇒M 5 Source⇒ M 5 Drain⇒M 6 Drain⇒M 7 Gate.

Because the original charge route passes many transistors, the charge speed is not fast and the rise time is a little long. Then the additional source follower circuit provides a new charge route to charge the output transistor ‘M7’ quickly as

(15)

V DD⇒M 7 Source⇒M 7 Gate⇒

Then the value of output current Iout is

M 10 Source⇒M 10 Drain⇒GN D.

W7 /L7 Iref W6 /L6 µp ·Cox (W7 /L7 )·(W8 /L8 ) = · ·(Vbase − VS8 − VT )2 . (16) 2 W6 /L6 Iout =

And the voltage drop from VDD to Vbase for CSM is VCSMdrop = VGS7 + VGS8 + VDS9 .

(17)

M 7 Source⇒V DD⇒M 5 Source⇒ M 5 Drain⇒M 10 Source⇒M 7 Gate. (21)

B. Source Follower Mode (SFM) The source follower architecture is often used to increase the driver capability, then the new LDD design introduces the architecture and proposes the “Source Follower Mode (SFM)” based on the idea of “Switch Position Modification” (Fig. 5). In Fig. 5 the original charge route is V DD⇒M 7 Source⇒M 7 Gate⇒M 10 Source⇒ M 10 Gate⇒M 9 Source⇒M 9 Drain⇒ M 8 Source⇒M 8 Drain⇒GN D.

Similarly, the voltage drop from VDD to Vbase for SFM is

(18)

As a result, the “Combination Switch Mode (CSM)” can decrease the fast switch on/off current and reduce the overshoot/undershoot influences. And the discharge route in the CSM architecture can also drop the waveform quickly and improve the slew-rate performance. The large output current can be realized by the current mirror architecture (Eq. (16)). Also the voltage drop in Eq. (18) is not very big and is controlled under the accepted constraint range.

(19)

(20)

Thus the large size transistor ‘M7’ can be charged faster and the rise time can also increase more rapidly by the new source follower charge route in Fig. 5. The discharge route is similar to the “Combination Switch Mode (CSM)” by the detailed expression of Eq. (21). And the discharge function for the SFM architecture also resembles the CSM LDD design as Fig. 4.

In the operation situation, the value of VDS9 is close to zero, then the voltage drop is decided by the output transistor ‘M7’ and the base transistor ‘M8’, or VCSMdrop ∼ = VGS7 + VGS8 .

The “Source Follower Mode (SFM)” LDD architecture.

VSF Mdrop

= VGS7 + VGS8 + VGS10 + VDS9 ∼ = VGS7 + VGS8 + VGS10 .

(22)

Then the “Source Follower Mode (SFM)” have more voltage drop than the “Combination Switch Mode (CSM)”. So the swing range of Vbase in SFM architecture is smaller than the CSM design, which limits the output current values and the applications of SFM architecture. Another disadvantage for SFM architecture is the small current distortion. Because the source follower supplies the additional charge route, the fast charge can improve the rise time characteristic. However, if the output current raises from the small current, the source follower charge capability is oversize and results in the large overshoot. Then the SFM architecture is not suitable for small output current situation. V. R ESULTS AND D ISCUSSIONS Because of the demerits of large voltage drop and small current deterioration, we adopted the “Combination Switch Mode (CSM)” instead of the SFM architecture as the final LDD architecture (Fig. 6(a)), where the Vbase is connected to

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(a) CSM LDD circuit schematic diagram. Fig. 6.

(b) CSM LDD circuit extended waveform.

(c) CSM LDD circuit global waveform.

The practical “Combination Switch Mode (CSM)” laser diode driver circuit diagram and characteristics.

VDD to keep the reference stability. The corresponding series transistor ‘M3’ is moved to the bottom of the reference transistor ‘M8’. And the parallel transistor ‘M5’ remains the original position of the CSM architecture to discharge the accumulated charge quickly. Moreover, the additional transistor ‘M4’ avoids the voltage floating and amends the LDD circuit performance. Under the experimental environments of SUN Blade 2500 and Cadence 5.0, we get the detailed output simulation results, including the local extended waveform (Fig. 6(b)) and the global current signal (Fig. 6(c)). The production technology for circuit simulation and chip design is 0.6-µm CMOS technology. The system voltage ‘Vdd’ is 4.5V, and the test input voltage ‘Vin’ has the appropriate frequency with 70ns period and 0.1ns slew-rate (rise time or fall time). By the comparison of the proposed circuit waveforms in Fig. 6 with the conventional LDD results in Fig. 2, we see that the proposed LDD circuit can improve the output current waveform greatly and send out better output current with high performance signal integrity to drive the laser diode device. For example, in the common output current 200mA, the rise time and fall time are 0.2ns for the proposed LDD circuit with switch position modification. However, for the conventional LDD circuit the rise time is about 0.4ns and the fall time is below 0.5ns (Fig. 2). Moreover, the proposed circuit has much smaller overshoot/undershoot values and costs only a few parasitic effects compared with the conventional circuit, such as 1.7% overshoot for the proposed LDD (Fig. 6(c)) and 47% overshoot for the conventional circuit at 200mA case as shown in Fig. 2(c). In addition, the chip area of the proposed circuit is also decreased greatly because the SPM method replaces large current output switch by small inside current switch before the output stage, such as the switch insertion positions of ‘M3’, ‘M5’ and ‘M6’ shown in Fig. 6(a). The experimental chip area indicates that the proposed LDD design can realize about 30% area improvement in the practical laser diode driver chip layout, which extends the application range of LDD circuit greatly. VI. C ONCLUSION We have designed a new LDD circuit for the large current and high speed laser diode driver with high performance output waveform in the 0.6-µm CMOS technology.

The proposed idea of “Switch Position Modification (SPM)” enables the large current output with low parasitic effects and efficient overshoot/undershoot/slew-rate characteristics. And the adopted “Combination Switch Mode (CSM)” architecture based on the introduced SPM idea also improves the circuit performance further and satisfy the practical LDD design requirements. Experimental results show that the present LDD circuit can decrease the chip area and improve the signal integrity greatly for the required output laser driver waveform. And the delicate driver circuit design also enables widespread production applications for the LDD circuit in the recent consumer electronics products. ACKNOWLEDGMENT The authors would like to thank T. Taguchi, T. Shiramatsu and M. Kuwahara of TOSHIBA Corporation for reference, discussion and test examples. And this work was supported in parts by funds from the MEXT via Kitakyushu and Fukuoka innovative cluster projects. R EFERENCES [1] K. Nishimura, S. Inui, M. Kurebayashi, T. Kaku, and A. Asada, “Highspeed DVD-multi drive system,” IEEE Trans. Consumer Electronics, vol. 50, no. 1, pp. 198-203, Feb. 2004. [2] J. Sturm, M. Leifhelm, H. Schatzmayr, S. Groiss, and H. Zimmermann, “Optical receiver IC for CD/DVD/blue-laser application,” IEEE J. SolidState Circuits, vol. 40, no. 7, pp. 1406-1413, July 2005. [3] M. Nourani and A. R. Attarha, “Detecting signal-overshoots for reliability analysis in high-speed system-on-chips,” IEEE Trans. Reliability, vol. 51, no. 4, pp. 494-504, Dec. 2002. [4] W. Rhee, B.-S. Song, and A. Ali, “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ∆Σ modulator,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1453-1460, Oct. 2000. [5] H. Lee, P. K. T. Mok, and K. N. Leung, “Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators,” IEEE Trans. Circuits Syst. II, vol.52, no.9, pp.563-567, Sept. 2005. [6] D. Kawamoto, H. Sekiya, H. Koizumi, I. Sasase, and S. Mori, “Design of phase-controlled class E inverter with asymmetric circuit configuration,” IEEE Trans. Circuits Syst. II, vol. 51, no. 10, pp. 523-528, Oct. 2004. [7] B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed., New York, NY: McGraw-Hill, 2001. [8] L. Dai and R. Harjani, “CMOS switched-op-amp-based sample-and-hold circuit,” IEEE J. Solid-State Circuits, vol.35, no.1, pp.109-113, Jan.2000. [9] G. K. Balachandran and P. E. Allen, “Switched-current circuits in digital CMOS technology with low charge-injection errors,” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1271-1281, Oct. 2002. [10] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 2nd ed., New York, NY: Oxford University Press, 2002.

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