USO0RE42403E

(19) United States (12) Reissued Patent

(10) Patent Number:

Babcock et al. (54)

(45) Date of Reissued Patent:

LATERALLY DIFFUSED MOS TRANSISTOR

(56)

U.S. PATENT DOCUMENTS 5,485,027 A *

(75) Inventors: Jeff Babcock, Santa Clara, CA (US);

1/1996

2 * 1%;

-

,

JOhan Agus Barmawan’ Cupemno’ CA

Williams et a1. ............ .. 257/343

gleflzelt

,

u]1 a

257649

.......................... ..

6,831,332 B2* 12/2004 D’Anna 613.1. ............. .. 257/343

(Us); John Mason, Sunnyvale, CA (Us) Assignee: RovecAcquisitions W1 ~ t DE SLtd.,LLC,

lmlng on,

May 31, 2011

References Cited

HAVING N+ SOURCE CONTACT TO N_DOPED SUBSTRATE

(73)

US RE42,403 E

6,864,533 B2

3/2005 Yasuhara et a1.

6,890,804 B1*

5/2005

Shibib et a1. ................ .. 438/163

7,087,959 7,119,399 B2* 10/2006 8/2006 Ma Shibib 6161. et a1. .......... ..

(U )

7,132,325 B2* 11/2006 Abadeer et a1. 7,518,169 B2*

4/2009 Taddiken

257/335 257/341 438/248 .. 257/288

(21)

APPl- NO-I 12/139,020

2005/0112808 A1*

(22)

Filed:

Jun. 13, 2008

2005/0280087 A1 * 2007/0034944 A1 * 2008/0023785 A1 *

1/2008

(Under 37 CFR1'47)

2008/0197411 A1*

8/2008 K016061511. ................. .. 257/343

Related US. Patent Documents Reissue of: (64) patent NO; 7,061,057 Issued; Jun, 13, 2006

Appl. No.1 Filed:

5/2005 Shibib et a1.

... 438/163

12/2005 Babcock et a1. 2/2007 Xu et a1. .......... .. Hebert ..... ..

257/343 257/335 257/492

* Cited by examiner Primary Examiner * Nathan W Ha (74) Attorney, Agent, or Firm * Sterne, Kessler, Goldstein

10/870,720 Jun. 16, 2004

& Fox P.L.L.C.

(57)

ABSTRACT

(51)

Int. Cl. H01L 29/76

(52)

U-s- Cl- ~~~~~~ ~~ 257/401; 257/328; 257/329; 257/330;

epitaxial layer on an N-doped semiconductor substrate and

257/342; 257/344; 257/408

using a trench contact for ohmically connecting the N-doped

(58)

Field Of Classi?cation Search ........ .. 257/3424344,

Reduced source resistance is realized in a laterally diffused

(200601)

MOS transistor by fabricating the transistor in a P-doped source region to the N-doped substratg

257/3284329, 330, 401, 408 See application ?le for complete search history.

29 Claims, 14 Drawing Sheets

_

Gate shleld

26 Source

[ 28 Gate shield

/—24 Dram

Shield-to-source Contacts

12 42

20 32

14

40 N+ Substrate 44

20 P-Epi 1015 crn‘3

P+ Buried layer 5 101 9cm'3

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US RE42,403 E 1

2 The invention and objects and features thereof will be more

LATERALLY DIFFUSED MOS TRANSISTOR HAVING N+ SOURCE CONTACT TO N-DOPED SUBSTRATE

readily apparent when the following detailed description and appended claims when taken with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

Matter enclosed in heavy brackets [ ] appears in the original patent but forms no part of this reissue speci?ca

FIG. 1 is a perspective view of a LDMOS transistor formed

tion; matter printed in italics indicates the additions made by reissue.

on a P-doped substrate with a source region and source con tact.

FIG. 2 is a perspective view of a LDMOS transistor with a n-doped substrate and a source region and source contact in accordance with an embodiment of the invention. FIGS. 3A-3L are section views illustrating the formation of a trench source contact to the n-doped substrate of the LDMOS transistor in FIG. 2.

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to co-pending applications Ser. No. 10/870,753, ?led Jun. 16, 2004, entitled LDMOS TRAN SISTOR WITH IMPROVED GATE SHIELD, Ser. No.

DETAILED DESCRIPTION OF THE ILLUSTRATE EMBODIMENTS

10/870,012, ?led Jun. 16, 2004, entitled LDMOS TRANSIS TOR HAVING GATE SHIELD AND TRENCH SOURCE

CAPACITOR, and Ser. No. 10/870,795, ?led Jun. 16, 2004, entitled LATERALLY DIFFUSED MOS TRANSISTOR HAVING INTEGRAL SOURCE CAPACITOR AND GATE

20

dance with the prior art. A P— doped epitaxial layer 12 is

SHIELD, all of which are incorporated herein by reference

formed on a P+ substrate 10 with the transistor structure

for all purposes. BACKGROUND OF THE INVENTION

This invention relates generally to semiconductor transis tors, and more particularly the invention relates to laterally diffused MOS (LDMOS) transistors. The LDMOS transistor is used in RF/microwave power

fabricated in and on epitaxial layer 12. The transistor com 25

a gate 18 formed over and spaced from P— channel region 20 extends from gate 18 to drain 16. A metal drain contact 24 contacts drain 16 and metal contact 26 contacts source 14 and 30

silicon layer (P—) on a more highly doped silicon substrate

(P+). A grounded source con?guration is achieved by a deep 35

which is grounded. (See, for example, US. Pat. No. 5,869,

875.) 40

backside contact to the P+ substrate can require expensive

It is desirable to have the source resistance as low as pos 45

sistor is determined inpart by the mobility of positive carriers, sensitive to the drain-source voltage (Vds) and its effects. Further, a metal such as a gold backside contact to P+ sub 50

In accordance with the present invention, a LDMOS tran sistor is fabricated on an N-doped substrate having a P-doped epitaxial layer grown on the substrate with a buried P-doped

reduces or overcomes the adverse effects on source resistance 55

A source contact is provided through the epitaxial layer and buried layer to the N-doped substrate. The contact also ohmi cally engages a P-doped channel region and a P+ sinker, if present. Thus, the electrical carriers are now electrons in the

and source contact.

strate 10 can require expensive preform compounds during packaging to maintain low source resistance. FIG. 2 is a perspective view of one embodiment of a LDMOS transistor in accordance with the invention which

layer in the epitaxial layer. The transistor is fabricated in the

without the need for preform compounds. Additionally, the drain extension region (the epitaxial layer and P buried layer) allows electrical junction isolation of the drain from the body

sible. As noted above, source resistance of the LDMOS tran or holes, in P+ substrate 10. The source resistance is also

SUMMARY OF THE INVENTION

N-doped substrate rather than holes in a P-doped substrate. Since electrons have higher mobility in a semiconductor than do holes, the source resistance is reduced. Further, a gold backside contact to the N-doped substrate is readily made

substrate 10. A source contact can be provided for the tran sistor on the backside of substrate 10. P+ sinker 32 is not

diffusion from the trench contact.

preform compounds during packaging to maintain low source

P-doped epitaxial layer.

connected with source electrode 26 through conductive ribs 30. Source contact 26 ohmically contacts N-doped source region 14 and an extension of P— doped channel region 20 and ohmically contacts P+ substrate 10 through a P+ doped sinker

needed in a low power application but helps prevent a deple tion region from the drain the sinker can be formed by out

drain-source voltage (Vds) and its effects. Further, a gold resistance. The present invention is directed to reducing or eliminating these characteristics with conventional LDMOS transistors.

an extension of the P-doped channel region 20. In this embodiment a gate shield 28 provides shielding between gate 18 and drain contact 24, and gate shield 28 is ohmically

32 which extends through P-doped epitaxial layer 12 to P+

The source resistance of the LDMOS transistor is deter

mined in part by the mobility of positive carriers, or holes, in the P+ substrate. The source resistance is also sensitive to the

prises a N-doped source region 14, a N-doped drain region 16, by a silicon oxide. A lightly doped drain drift region 22

ampli?ers. The device is typically fabricated in an epitaxial P+ sinker diffusion from the source region to the P+ substrate,

FIG. 1 is a perspective view of a LDMOS transistor. The transistor is fabricated on a P-doped substrate 10 in accor

60

in the conventional LDMOS transistor structure using a P+ substrate. Like elements of the transistors in FIGS. 1 and 2 have the same reference numerals. In this embodiment, the P+ substrate 10 is replaced by an N+ substrate 40 and P+ sub strate 10 of FIG. 1 in effect becomes a P+ buried layer 42 in P-epitaxial layer 12 as shown in FIG. 2. In order for source contact 26 to ohmically contact N+ substrate 40, a trench is

etched through a central portion of P— region 20 and the underlying P+ sinker region 32 into N+ substrate 10, and then the groove is ?lled with conductive material including a metal 65

silicide 44 and the metal source contact 26. Source contact 26

and silicide layer 44 ohmically contact source region 14 as in the prior art structure of FIG. 1.

US RE42,403 E 4

3 Fabrication of the N+ source trench contact to the under

[c)] a gate electrode on a dielectric layer on the surface of

lying N+ substrate is readily implemented using conventional

the P-doped epitaxial layer and over a P-doped channel

semiconductor processing. FIGS. 3A-3K are section views illustrating the fabrication of the trench contact after the

region in the P-doped epitaxial layer[,]; [d) a] an N-doped drain region in the P-doped epitaxial

source region 14, drain region 16, channel region 20, gate 18, and drift region 22 have been fabricating using conventional semiconductor processing. While not part of the invention, it will be noted that drain region 16 includes a highly doped surface region for contact purposes, and underlying N-doped region, and the N— drift region 22. Further, the lightly doped

layer extending from one side of the gate electrode[,]; [e) a] an N-doped source region in the P-doped epitaxial layer extending from an opposing side of the gate elec

trode[,]; and [f)] a source contact extending through the P-doped epi taxial layer and the P+ buried layer into the N-doped substrate and connecting the N-doped source region to the N-doped substrate. 2. The LDMOS transistor [as de?ned by] of claim 1,

channel region 20 extends from under gate 18 to an adjacent transistor and under its gate 18'. Source region 14 extends to the adjacent transistor, also, with the source contact (to be

wherein the source contact electrically contacts the N-doped

fabricated) shared by both adjacent transistors. In FIG. 3A surface layers of silicon oxide 50, silicon nitride

source region and the P-doped channel region. 3. The LDMOS transistor [as de?ned by] of claim 2 [and],

52, and silicon oxide 54 have been fabricated over the surface of the transistor structure. A photoresist mask 56 is formed over the surface layers, and as shown in FIG. 3B silicon oxide

N-doped substrate. 4. The LDMOS transistor [as de?ned by] of claim 3,

layers 50, 54 and silicon nitride 52 are removed by etching

further including a backside source contact on a surface of the

20

over source region 14. Resist 56 is then stripped and the

wherein the source contact is formed in a groove extending

exposed silicon is then selectively etched through source

from the surface of the P-doped epitaxial layer through the P-doped epitaxial layer and the P+ doped buried layer to the

region 14, channel region 20, P+ sinker region 32 (if present),

N-doped substrate, and includes a metal silicide layer formed

P+ layer 42, and into N+ substrate 40, as shown in FIG. 3C. In FIG. 3D, photoresist mask 58 is formed over the surface, and the oxide layers 50, 54 and nitride layer 52 above drain 16 are removed by etching, and then a thin layer of exposed silicon (e.g., 100 A) is etched from the exposed source contact region and the drain contact region. In FIG. 3E, a silicon oxide deposition and etch back provides silicon oxide spacers 60 for

25

on the surface of the groove and a ?ller metal ?lling the groove.

5. The LDMOS transistor [as de?ned by] of claim 4, wherein the ?ller metal comprises gold. 6. The LDMOS transistor [as de?ned by] of claim 5, 30

the drain contact area and spacers 62 for the source contact

wherein the metal silicide comprises a refractory metal sili cide.

area. However, use of spacers is not required in practicing the

7. The LDMOS transistor [as de?ned by] of claim 6 [and], further including a gate shield overlying a portion of the gate

process. A silicide contact 64 is formed on the surface of drain 16, and silicide contact 66 is formed on the surface of the groove for the source contact. Thereafter, as shown in FIG.

electrode facing the N-doped drain region. 8. The LDMOS transistor [as de?ned by] of claim 7, 35

wherein the gate shield is electrically connected to the source

3F, a metal layer 68 (TiWiTiWNiTiW) is formed over the surface of the structure and includes a gold seed layer for

contact.

subsequent gold deposition and also provides a shield struc

wherein the gate electrode is electrically connected to the source contact by conductive ribs overlying the gate contact.

9. The LDMOS transistor [as de?ned by] of claim 8,

ture for the gate. In FIG. 3G, a photoresist mask 70 is formed

over the surface, and then gold is plated onto the exposed gold seed layer of metal layer 68 to form source contact 26 and drain contact 24, as shown in FIG. 3H. The plated gold does not stick to the photoresist mask. Photoresist mask 70 is removed as shown if FIG. 3I, and then as shown in FIG. 3] another photoresist mask 72 is formed over the surface to expose selected portions of metal

40

10. The LDMOS transistor [as de?ned by] ofclaim 9 [and], further including a drain contact to the N-doped drain region.

45

11. The LDMOS transistor [as de?ned by] of claim 10, wherein the N-doped drain region includes a lightly-doped drain region extending from a more heavily doped drain region to the channel region, the drain contact engaging the more heavily doped drain region.

layer 68 abutting drain contact 24, which is then removed by

12. The LDMOS transistor [as de?ned by] ofclaim 4 [and],

etching as shown in FIG. 3K. Mask 72 is then removed as shown in FIG. 3L with the LDMOS transistor and contact

further including a gate shield overlying a portion of the gate

structures completed. The portion of metal layer 68 over gate

50

18 and facing drain contact 24 functions as a gate shield in this embodiment.

wherein the gate shield is electrically connected to the source contact.

The use of an N+ substrate in the LDMOS structure pro

vides advantages in reducing source contact resistance as described above. While the invention has been described with

14. The LDMOS transistor [as de?ned by] of claim 13 [and], further including a drain contact to the N-doped drain 55

region.

60

15. The LDMOS transistor [as de?ned by] of claim 14, wherein the N-doped drain region includes a lightly doped drain region extending from a more heavily doped drain region to the channel region, the drain contact engaging the more heavily doped drain region.

reference to a speci?c embodiment, the description is illus trative of the invention, and is not to be construed to be as

limiting of the invention. Various modi?cations and applica tions may occur to those skilled in the art without departing from the true spirit and scope of the invention as de?ned by

the appended claims.

electrode facing the N-doped drain region. 13. The LDMOS transistor [as de?ned by] of claim 12,

16. A transistor structure comprising:

[a) a] an N-doped semiconductor substrate[,]; What is claimed is: 1. A LDMOS transistor comprising:

[a) a] an N-doped substrate[,]; [b)] a P-doped epitaxial layer on the N-doped substrate with a P+ doped buried layer in the epitaxial layer[,];

[b)] a P-doped epitaxial semiconductor layer formed on the substrate, the layer including a buried P-doped layer and

having a surface[,]; [c)] a source region and a drain region formed in the epi

taxial layer with a channel region there between[,];

US RE42,403 E 6

5

23. A device, comprising: a doped substrate; a doped epitaxial layer over the doped substrate, wherein the doped epitaxial layer includes a doped buried layer; a doped source region in the doped epitaxial layer; and

[d)] a gate electrode formed on an insulator above the

channel region[,]; and [e)] a source contact extending from the surface of the

epitaxial layer through the epitaxial layer to the N-doped semiconductor substrate, the source contact including a

trench through the epitaxial layer ?lled With conductive

a source contact, wherein the source contact extends

material.

through the doped epitaxial layer into the doped sub

17. The transistor structure [as de?ned by] of claim 16, Wherein the semiconductor substrate is grounded during

strate and connects the doped source region to the doped substrate. 24. The device of claim 23, wherein the source contact

device operation, the source contact extending ground to the source region.

18. The semiconductor structure [as de?ned by] of claim

comprises a trench through the doped epitaxial layer.

16, Wherein the transistor comprises a laterally diffused MOS transistor. 19. The transistor [device as de?ned by] structure ofclaim

25. The device ofclaim 24, wherein the trench is?lled with conductive material.

26. The device ofclaim 23, wherein: the doped substrate is an N-doped substrate;

18, Wherein the drain region includes a heavily doped region and a lighter doped drift region extending to the channel

the doped epitaxial layer is a P-doped epitaxial layer; and

region.

the doped source region is an N-doped source region.

20. The transistor structure [as de?ned by] of claim 19,

27. The device ofclaim 26, wherein the doped buried layer

Wherein the insulator under the gate electrode extends over

the drift region. 21. The transistor structure [as de?ned by] of claim 16,

20

Wherein the conductive material is selected from the group

22. The transistor structure [as de?ned by] of claim 21, con.

28. The device ofclaim 23, wherein the doped buried layer is between the doped substrate and the doped epitaxial layer. 29. The device of claim 23, wherein the source contact

consisting of polysilicon, a refractory metal, and a refractory

extends through the doped buried layer.

metal silicide.

Wherein [said] the gate electrode comprises doped polysili

is a P-doped buried layer.

25

UNITED STATES PATENT AND TRADEMARK OFFICE

CERTIFICATE OF CORRECTION PATENT NO.

I RE42,403 E

APPLICATION NO.

: 12/139020

DATED

: May 31, 2011

INVENTOR(S)

: Babcock et a1.

Page 1 ofl

It is certified that error appears in the above-identi?ed patent and that said Letters Patent is hereby corrected as shown below:

Column 5, line 11, in Claim 18, delete “semiconductor structure” and insert -- transistor structure --.

Signed and Sealed this Tenth Day of July, 2012

David J. Kappos Director 0fthe United States Patent and Trademark O?ice

24 Dram

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